I'm confused if I can use polar capacitor at c7. Lets say I input a sine wave(A = 1V, Offset = Vcc/2) at R7 at one half cycle the pin A of the capacitor will be at higher voltage and another half cycle pin B of the capacitor will be at higher voltage. What I don't understand is that at one half cycle when the capacitor is reversed biased, it won't perform as expected and I can't find non-polar capacitors with such high capacitances. Am I missing something?Any help is highly appreciated.

 

Why can't you find 10 µF non-polarized capacitors?

DigiKey has, literally, thousands of different choices to choose from -- and that's if you limit yourself to just ceramic capacitors.

10 µF Ceramic Capacitors | Electronic Components Distributor DigiKey

 

Because the signal is referenced to 0V at the input and half supply on the op-amp one plate will always be more positive than the other, so a polar capacitor will be OK.

This looks like an audio application, and no-one in their right mind would use a X5R dielectric for audio, and C0G don't exist at 10uF. The op-amp probably isn't the best choice, but a X5R ceramic capacitor would be worse.
Film capacitors are suitable, but 10uF film capacitors tend to be rather large. I would use an aluminium electrolytic, only because the cutoff frequency of the high-pass filter it forms with R7 is well below the audio frequency range.

 

Because the signal is referenced to 0V at the input and half supply on the op-amp one plate will always be more positive than the other, so a polar capacitor will be OK.

I'm not following this. If the input signal is (as stated) a 1 V amplitude sinusoid with an offset of Vcc/2, then it will be going above and below Vcc/2. Since the voltage on the opamp side is clamped at Vcc/2 (provided the opamp is operating in the active region), then the polarity of the voltage across the capacitor will alternate.

It would be nice to see a bit more of the input side of the schematic. I don't see anything that says that the left side of the capacitor is restricted to voltages below Vcc/2.

 

What he is missing is that with a gain of 220, and an output limited to 5V p/p, inputting a 1V peak signal isn't the wisest thing to do. I did make the assumption that an audio circuit with a ground-referenced output probably had a ground-referenced input.
If the 1V signal was >11kHz (to keep it within linear operation) C7 will be a dead short to AC, the only voltage across it will be the DC offset between Vcc/2 and input ground.

 

There is the option of the bipolar electrolytic
https://www.mouser.co.uk/ProductDet...=sGAEpiMZZMvwFf0viD3Y3ffldXPLozay4OyhjlgoKuU=

 

What he is missing is that with a gain of 220, and an output limited to 5V p/p, inputting a 1V peak signal isn't the wisest thing to do. I did make the assumption that an audio circuit with a ground-referenced output probably had a ground-referenced input.
If the 1V signal was >11kHz (to keep it within linear operation) C7 will be a dead short to AC, the only voltage across it will be the DC offset between Vcc/2 and input ground.

I was trying to give an example, let me rephrase ( lets say the voltage rails are at (-10, 10) and assume it to be an ideal op-amp and gain is lets say 3 and Input is (A=1, offset = Vcc/2) ) won't then the polarity across the cap will be positive on one cycle and negative on another cycle?
I'm apologise for bothering but I'm confused as hell rn.

 

If the voltage rails are -10V and +10V then all bets are off, because the LMV321 is dead.

 

Here's the simulation:
Green is output.
Blue is input.
Red is the voltage after the capacitor.
At 1kHz, the capacitor is effectively a dead short to AC (its impedance is 15Ω)
The input current is 1V/10k = 100uA.
So the AC voltage across the capacitor is 100uA * 15Ω = 1.5mV
You can see that the DC voltage across the capacitor is the difference between red and blue, which remains at +5V DC (±1.5mV)

 

Assuming that the DC voltage level at the left hand end of R7 is zero volts then the steady state voltage across the capacitor will be vcc /2 (Let's say 5 volts.) the right hand end being positive. If the input sine wave was a VERY low frequency what you are thinking would be true. Assuming that this is an audio application the input frequency is not likely to be less than 20 hz.
At 20 hz the 10 uF capacitor will have a reactance of about 800 ohms. If the input sine wave at the left hand end of R7 is 1 volts RMS then we have 1 volt across 10800 ohms. (This is not quite right as I should have used vector addition bit the error will be very small.) so the voltage across the capacitor will be 1 x 800/1080 = 0.074 volts. RMS ( Peak = 0.105 volts.) So the voltage across the capacitor will be 5.105 volts at the negative peak of the input sine wave. On the positive peak it will be 4.895 volts. So there is never any reverse polarity across the capacitor.

Les.

 

Here's the simulation:
View attachment 316134Green is output.
Blue is input.
Red is the voltage after the capacitor.
At 1kHz, the capacitor is effectively a dead short to AC (its impedance is 15Ω)
The input current is 1V/10k = 100uA.
So the AC voltage across the capacitor is 100uA * 15Ω = 1.5mV
You can see that the DC voltage across the capacitor is the difference between red and blue, which remains at +5V DC (±1.5mV)

This was very insightful, thank you.

 

I was trying to give an example, let me rephrase ( lets say the voltage rails are at (-10, 10) and assume it to be an ideal op-amp and gain is lets say 3 and Input is (A=1, offset = Vcc/2) ) won't then the polarity across the cap will be positive on one cycle and negative on another cycle?
I'm apologise for bothering but I'm confused as hell rn.

The ultimate bottom line is that you need to avoid applying a reverse polarity voltage to a polarized capacitor (unless the capacitor is specifically specified to be able to tolerate it). At the very least, doing so will almost certainly result in undesired circuit performance as the effective device parameters can deviate markedly from what you expect, but it can also result in destructive behavior.

However, this is frequently accomplished by adding a sufficient DC bias to the capacitor. When doing so, you now need to ensure that any AC signal that the device will see will never be large enough to overcome the DC bias. You can always imagine some hypothetical signal that will do this, but can that signal actually ever be applied to the circuit in question? That's what matters. So you need to determine what the maximum allowed signal is that you can tolerate, and what the maximum allowed signal is that you have to accommodate for the circuit to function as desired, and keep the latter comfortable smaller than the former.