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Hi,
I have a PCB layout for camera sensor that runs at 768 Mbps with 2 data lanes as shown below:
Unfortunately, the sensor and controller pins layout is such that no matter how I route these differential pairs, they will always cross. However I tried to do it with controlled impedance and over very short distance. Each pair is no longer than 9mm.
Despite this, I am unbale to lock even a single data frame from the sensor. Can be a software issue, but Gemini also shed some light on my layout saying "there is no stitching vias near layer to layer transitioning vias therefore signal integrity is all messed up".
Here is my stuckup:
L1: Red signals
L2: Solid ground plane (not shown)
L3: Patch of solid ground plane covering the signals shown (not shown)
L4: Blue signals
How likely is it that my layout is responsible for breaking the communication here?
Thank you.
I have a PCB layout for camera sensor that runs at 768 Mbps with 2 data lanes as shown below:
Unfortunately, the sensor and controller pins layout is such that no matter how I route these differential pairs, they will always cross. However I tried to do it with controlled impedance and over very short distance. Each pair is no longer than 9mm.
Despite this, I am unbale to lock even a single data frame from the sensor. Can be a software issue, but Gemini also shed some light on my layout saying "there is no stitching vias near layer to layer transitioning vias therefore signal integrity is all messed up".
Here is my stuckup:
L1: Red signals
L2: Solid ground plane (not shown)
L3: Patch of solid ground plane covering the signals shown (not shown)
L4: Blue signals
How likely is it that my layout is responsible for breaking the communication here?
Thank you.
