Will this IC break if frequency is adjusted while its powered in a half bridge using a variable capacitor?

https://www.infineon.com/dgdl/ir2153.pdf?fileId=5546d462533600a4015355c8c5fc16af

 

Based on functional block diagram seems like freq change
does not alter basic timing relationships of the part, ie. dead time
for example. But that seems to be qualified by how freq is changed,

By variable cap you men hand operated cap ? If so I think you
should be OK.

I would contact vendor FAE on that question just to be sure something
not discussed in oscillator/logic that may bite you.


Regards, Dana.

 

The datasheet has a number of revs. Here is one showing
some gate drive capability -

https://www.jameco.com/Jameco/Products/ProdDS/1563930.pdf





Regards, Dana.

 

Wouldn't it be better to use a pot instead of a variable cap to change frequency? Isn't that the normal way of doing things?

 

Would shoot-thru happen with a pair of identical discrete drivers?

In a production environment a discrete or IC based design will have
variation, so need for dead time generation very important. Even the
MOSFETS do not have exact same gate charge affecting switching time)
from one device to another.

Also if they were identical they would in fact have shootthru as their transition
would intersect at mid supply, basically showing both MOSFETS in a vertical
leg would be on.

If you use a modern UP with PWM (which has deadtime configuration) or a driver that
has internal dead time design implementation this problem goes away.


Regards, Dana.

 

It does have dead time, but based on datasheet its not clear if that is
fixed or a f() of frequency (I am thinking the latter is true).



And is it enough for the design ? For the specific MOSFETS being used ?


Regards, Dana.

 

This can be done with a processor pretty easily. As one changes the freq
it also changes the dead time settings in the PWM. Pretty simple actually.
Also can take pot input as freq changer.

See attached.

Probably takes ~ 15 - 20 lines of code.

What is the freq range you want and resolution of duty cycle ?



Regards, Dana.

 

The PIC micro 18F4431 can adjust that delay, IIRC, for 6 PWM outputs.

 

I haven’t seen the frequency range you’re trying to create?

 

Depends on what you are doing. Designs can be completely codeless,
eg. simple logic design, to very complex in coding.

The example I posted earlier requires code to take SAR output, write it to
PWM period register, and adjust the dead band values for the change in freq
to keep the values of dead time same in absolute time. The write to period
reg could be done by DMA, eg. automatic. But the dead time has to have
some code to calculate needed values.

It might be possible to use a table of ADC and Dead Time values, and do this
also with DMA. Making the whole design almost codeless except for a _Start()
instruction needed for SAR and one for PWM. And the DMA setup code, from
the DMA wizard code generator.

DMA is a little more complicated to setup because of all its parameters and
adjustments for endianess, bytes per burst, number bursts, addresses.....

So as stated in prior post I am thinking 10 - 20 lines of code.

Frequency range you want ? Does design also need its duty cycle changed ?
If so relationship between frequency and duty cycle, or are they independent ?


Regards, Dana.

 

Another approach (one chip, pot or rotary encoder external of course) -




Regards, Dana.

 

The output at ~ 22 Khz -



Regards, Dana.

 

For the heck of it I did design with lower end part, PSOC 4, and it seems to be a better
overall design to me. Uses lot less resources, leaves plenty of other capability available
for use, like LCD, DAC, Counters, Logic......




Regards, Dana.

 

3 Pins, one for POT input to A/D, the other 2 for the PWM outputs.

The CY8C4014 can possibly be used because it does have a Capsense A/D,
I have not tried this before however looks like it would work. Note resolution
limited to 7 bits, so that affects step size of frequency for the PWM control.


Regards, Dana.

 

Note to use Capsense A/D it needs an additional pin for Cmod capacitor.

Also the POT has to be physically close to part due to way Capsense A/D does
its conversions by using a HiZ V to I resistor at pin. This causes pin to "operate"
in a HiZ environment, therefore subject to noise pickup.



Regards, Dana.

 

Your question simply not complete, meaning what frequency do you
need, do they all need to be in phase, are they fixed or need to be
programmable, what resolution, accuracy.

It would hep if you describe system, overall requirements, functionality.

Otherwise answer can be shallow and not very meaningful.

Obviously every GPIO pin on the part can be, under software control
a square wave, and that has answered nothing.


Regards, Dana.