Hello! I am quite new to hardware memory mapping on microprocessors.

Z80 has 16 address lines, ROM has 13 and RAM has also 13.
I would use the A13 + MREQ with de-multiplexer to select each memory chip.

My question is: Can I use 8k ROM and 8k RAM in this configuration with Zilog 80?

 

You won't be able to run CP/M on it.

 

You won't be able to run CP/M on it.

Oh, I want to run my own software, not CP/M.
For start, I want to blink some LEDs with the software on the EEPROM.
I just want to know if it is possible to use the circuit I made above.

 

Maybe you can try to do a complete decode.

 

Maybe you can try to do a complete decode.

can you please tell me what do you mean by "complete decode"?
I was also curious how can I use I/O, coz it looks like data bus is accessing memory all the time and has no room for LEDs/buttons etc.

 

U2 6264 RAM has /CE1 and CE2.
There is nothing gained by driving both from the same CS signal. Keep one of them always active.

 

can you please tell me what do you mean by "complete decode"?

Your ROM and RAM are each 8K.
Hence organize your CHIP SELECT into eight 8K blocks. Use three address bits, A15-A13, using one 74LS138.

 

U2 6264 RAM has /CE1 and CE2.
There is nothing gained by driving both from the same CS signal. Keep one of them always active.

thanks! so I will just tie CS high all the time, and control it with CS'

 

Your ROM and RAM are each 8K.
Hence organize your CHIP SELECT into eight 8K blocks. Use three address bits, A15-A13, using one 74LS138.

what is the purpose of that?
and also, how can I use the I/O? It looks like Z80 is accessing ROM/RAM. F.e., I want a code in ROM to blink an LED on one data pin. how could I do that?

 

what is the purpose of that?
and also, how can I use the I/O? It looks like Z80 is accessing ROM/RAM. F.e., I want a code in ROM to blink an LED on one data pin. how could I do that?

Because one of these days you may want to add more ROM and RAM.

 

Because one of these days you may want to add more ROM and RAM.

ok!

 

In blue, A13 directly to /CE ROM and A13 to CE RAM, and /CE to ground. ROM and RAM will fill all memory addresses.
In red, remove inverter, and CE to +5V. Addresses=(ROM, RAM, nothing, nothing) repeat throughout memory space.

 

In blue, A13 directly to /CE ROM and A13 to CE RAM, and /CE to ground. ROM and RAM will fill all memory addresses.
In red, remove inverter, and CE to +5V. Addresses=(ROM, RAM, nothing, nothing) repeat throughout memory space.
View attachment 285051

well, I want the CPU to access memory when it actually wants, not everytime as you have shown in this scheme. thats why I do utilize the MREQ' output.I tinkered with the circuit some more:

 

My question is: Can I use 8k ROM and 8k RAM in this configuration with Zilog 80?

Hi Mayas,
Your original circuit is already accessing 8k ROM and 8K ROM, Addr A0 thru A12, and the LS139.

What changes to the circuit are you asking for.?
E

 

thats why I do utilize the MREQ' output.

Yes you are right. I forgot.

Are you going to write to the EPROM?

 

Yes you are right. I forgot.

Are you going to write to the EPROM?

no. That is why WE' is tied HIGH on it.

 

In about 1980 I had a "boot loader" program that load a program into ROM from the serial port. There was some peek and poke commands that made trouble shooting easy.

 

can you please tell me what do you mean by "complete decode"?
I was also curious how can I use I/O, coz it looks like data bus is accessing memory all the time and has no room for LEDs/buttons etc.

To find 8255 or some 74LS374, 74LS244, 74LS245.