I calculated all the values as below
\[
\text{Assume Q2 in saturation} \\
V_{CE} = 0.2V \\
V_{CC} - I_CR_C = V_{CE} \\
I_C = \frac{V_{CC} - V_{CE}}{R_C} \\
I_C = \frac{24V - 0.2V}{120\Omega} = 0.198A = 198mA \\
I_{B,min} = \frac{I_C}{\beta2} = \frac{198mA}{25} = 7.92mA \\
I_C + I_B = I_E \\
I_B = 100mA - 198mA = -98mA \\
\text{Hence Q2 is not in saturation} \\
\text{Q2 cannot be cutoff as base current is flowing and hence it is in active region} \\
I_{C2} + I_{B2} = I_{E2} ;\\
I_{C2} = \beta2I_{B2} \\
\alpha2 = 0.96 => \beta2 = 24 \\
25I_{B2}=100mA => I_{B2} = \frac{100mA}{25} => 4mA \\
I_{C2} = \beta2*I_{B2} = 24*4mA = 96mA \\
I_{E1} = -I_{B2} = -4mA \\
\text{Q1 in Active region} \\
I_{B1} + I_{C1} = I_{E1} \\
I_{B1} + \beta1I_{B1} = 4mA \\
50I_{B1} = 4mA => I_{B1} = 0.08mA \\
I_{C1} = 49*0.08mA = 3.92mA \\
V_{CE} = V_{CC} - I_CR_c \\
V_{CE} = 24V - (I_{C1} + I_{C2})*R_C;
V_{CE} = 24V - (3.92mA + 96mA)*120 \Omega\\
V_{CE} = 24V - 11.99V = 12V \\
\frac{I_C}{I_B} = \frac{99.92mA}{0.08mA} = 1249 ; \\
\frac{I_C}{I_E} = \frac{99.92mA}{100mA} = 0.992 ; \\
\]
I tried to verify using LTspice but the initial step is failing i tried to generate Ib1 of 0.08mA using a 5V source but the simulation shows around
0.065mA. Why there is difference of 0.08mA - 0.065mA = 0.015mA? ( I am following Integrated electronics Millman - Halkias textbook)

 

May I ask you: Why did you start with the assumptin that Q2 would be in saturation?

 

May I ask you: Why did you start with the assumptin that Q2 would be in saturation?

I just followed the procedure to ensure it is not in saturation like the other problems. Should i have avoided it, i am not sure if it is obvious.

 

I just followed the procedure to ensure it is not in saturation like the other problems. Should i have avoided it, i am not sure if it is obvious.

Didn`t you realize that the current Ie is given? From tis, you can calculate Vce for Q2.

 

if the Ic=198mA, how do you explain Ie=100mA?
Ic cannot be more than Ie in this circuit. and Vce is not 0.2V. you are off by a mile...

 

Didn`t you realize that the current Ie is given? From tis, you can calculate Vce for Q2.

But there is no direct formula to calculate VCE from iE. From my understanding I can calculate using VCC - IC*RC , so I need IC.

 

if the Ic=198mA, how do you explain Ie=100mA?
Ic cannot be more than Ie in this circuit. and Vce is not 0.2V. you are off by a mile...

The 198mA is only to prove transistor not in saturation, actual value is 96mA.

 

my bad... i skipped a lot. your match checks out. your simulation is off because your base current is off... 5V and R2 are not biasing Q1 the same way as your calculation.
adjust the value or simply replace input source from voltage to current type and things will match better.

 

Let's do a quick sanity check and see how it compares with your results.

If α is defined as Ic/Ie, and ß is defined as Ic/Ib, then since Ie = Ic + Ib we have

ß = α / (1-α) ≈ 1 / (1-α)

So

ß1 ≈ 1/(1 - 0.98) = 1/0.02 = 50
ß2 ≈ 1/(1 - 0.96) = 1/0.04 = 25

We also know that the effective current gain of a Darlington configuration is

ß ≈ ß1·ß2 = 50·25 = 1250

This agrees with your results, but your final line doesn't. Look at it very carefully and see if you can spot the somewhat glaring math error you made. It disagrees with your combined ß by an order of magnitude.

 

I tried to verify using LTspice but the initial step is failing

When you try to confirm/verify your results, you must use a transistor model which contains the parameter (alpha) you have used in your calculation. Other wise, it would be no surprise to get large differences between calculation and simulation.
What you could do is the following: Start a new calculation with the beta values (resp. alpha) derived from the used LTSpice models - and compare both results.

 

hi V123,
This is your asc file.
Posted to show you how to use the method of multi-line model definitions text on your file text.
Use the '+' symbol to start a new line of text.

You can also copy and paste the model text into the standard.bjt text file
Usually located at C:\Users\xxxx\Documents\LTspiceXVII\lib\cmp

Note I have used a current source at Q1 Base input.
E

 

View attachment 363983
I calculated all the values as below
\[
\text{Assume Q2 in saturation} \\
V_{CE} = 0.2V \\
V_{CC} - I_CR_C = V_{CE} \\
I_C = \frac{V_{CC} - V_{CE}}{R_C} \\
I_C = \frac{24V - 0.2V}{120\Omega} = 0.198A = 198mA \\
I_{B,min} = \frac{I_C}{\beta2} = \frac{198mA}{25} = 7.92mA \\
I_C + I_B = I_E \\
I_B = 100mA - 198mA = -98mA \\
\text{Hence Q2 is not in saturation} \\
\text{Q2 cannot be cutoff as base current is flowing and hence it is in active region} \\
I_{C2} + I_{B2} = I_{E2} ;\\
I_{C2} = \beta2I_{B2} \\
\alpha2 = 0.96 => \beta2 = 24 \\
25I_{B2}=100mA => I_{B2} = \frac{100mA}{25} => 4mA \\
I_{C2} = \beta2*I_{B2} = 24*4mA = 96mA \\
I_{E1} = -I_{B2} = -4mA \\
\text{Q1 in Active region} \\
I_{B1} + I_{C1} = I_{E1} \\
I_{B1} + \beta1I_{B1} = 4mA \\
50I_{B1} = 4mA => I_{B1} = 0.08mA \\
I_{C1} = 49*0.08mA = 3.92mA \\
V_{CE} = V_{CC} - I_CR_c \\
V_{CE} = 24V - (I_{C1} + I_{C2})*R_C;
V_{CE} = 24V - (3.92mA + 96mA)*120 \Omega\\
V_{CE} = 24V - 11.99V = 12V \\
\frac{I_C}{I_B} = \frac{99.92mA}{0.08mA} = 1249 ; \\
\frac{I_C}{I_E} = \frac{99.92mA}{100mA} = 0.992 ; \\
\]
I tried to verify using LTspice but the initial step is failing i tried to generate Ib1 of 0.08mA using a 5V source but the simulation shows around
0.065mA. Why there is difference of 0.08mA - 0.065mA = 0.015mA? ( I am following Integrated electronics Millman - Halkias textbook)

Hi,

I don't think you should assume either transistor is in saturation. There's nothing there to suggest that.

If you work backwards through the circuit you can calculate everything required exactly.
Start with the KNOWN emitter current of 100ma (they give as -100ma because they have the direction reversed for Ie).
You also know that:
Beta=B=a/(1-a)
so you can immediately calculate B2 which is the Beta for Q2.
Once you have that, you can use your known formula with base current:
Ic2=Ib2*B2
and please note that this is the collector current in Q2 only.
You also know:
Ie2=Ic2+Ib2
so:
Ie2=Ib2*B2+Ib2
and solving for Ib2:
Ib2=Ie2/(B2+1)

Now after that you will have a numerical value for Ib2, and since that is also Ie1, you can calculate Ib1 and Ic1 from that in the same way you did Q2 above.

One you get Ic1 and Ic2 you can add them:
Ic=Ic1+Ic2
and that is the total current through Rc.
Now that you know the current through Rc, you can calculate the voltage drop:
vRc=Rc*Ic
and now the collector voltage:
Vc=Vcc-vRc

Now you can compare that with an estimate of a bipolar transistor in saturation and determine if Q2 is in saturation or not.
You should then, using Vc, determine if Q1 is in saturation or not. Q1 has a slightly different vCE voltage than Q2 so it's a good idea to check that one too.

Now if this circuit was designed the way a lot of circuits like this are, the collector voltage would be close to Vcc/2 which is 12v for this circuit. That's not mandatory though. Once you calculate Vc you will know for sure.

So the idea is to take everything you know and try to use it to calculate a result. Because you are not given any base currents only the Q2 emitter current, you have to work backwards through the circuit to get the base currents and collector currents so you can use the subtraction of Vcc minus the drop of the collector resistor in order to get the collector voltage.

Give that a shot and see what you can come up with. Sometimes you have to sit down and look over the circuit and THINK about what might be happening, and that might give you an idea of how to proceed with the analysis. That could be why you have a little difficulty with some of these circuits. We like to have formulas that apply to everything but that's not the way it works. We have formulas for some things, then we have to figure out how to apply them.

 

Because you are not given any base currents only the Q2 emitter current, you have to work backwards through the circuit to get the base currents ............

Please forgive me for the following – not particularly important – remark:
Why “backwards”?
In accordance with physical logic, the base current Ib=Ie-Ic, as a small percentage of the emitter current Ie, is the result of the DC operating point that is established (Ib is not the cause of Ie).
This means that these considerations are actually “forward-looking.”

By the way: That`s the classical sequence for designing a gain stage:
* Select Vcc, Rc and Ic (transconductance gm=Ic/Vt) for realizing the required gain value ;
* Design the corresponding base biasing (with consideration of Ib - if known and/or necessary)

 

This transitional configuration is known as a Darlington pair.
And for this configuration, Vce voltage cannot be smaller than Vce1 + Vbe2


Therefore, the minimum Vce voltage will be around Vce1(sat) + Vbe2 = 0.8V assuming Vce1(sat) = 0.2V and Vbe2 = 0.6V
And because of this, Q2 will never be saturated.
As for the exercise, we know Ie2 = 100mA and α1 = 0.98, α2 = 0.96.
So we have:
Ic2 = Ie1 * α2 = 100mA * α2 = 96mA
And from there we see that:
Ib2 = Ie2 - Ic2 = 4mA
Ib2 = Ie1, so Ic1 = 4mA*α1 = 3.92mA
This means that:
Ic = Ic1 + Ic2 = 3.92mA + 96mA = 99.92mA ≈ 100mA
Vce = 24V - 120Ω*100mA = 12V
And the simulation results you are getting are different from hand calculations because the model LTspice is using is a much more sophisticated one.
You shoud use a much simpler model

 

Please forgive me for the following – not particularly important – remark:
Why “backwards”?
In accordance with physical logic, the base current Ib=Ie-Ic, as a small percentage of the emitter current Ie, is the result of the DC operating point that is established (Ib is not the cause of Ie).
This means that these considerations are actually “forward-looking.”

By the way: That`s the classical sequence for designing a gain stage:
* Select Vcc, Rc and Ic (transconductance gm=Ic/Vt) for realizing the required gain value ;
* Design the corresponding base biasing (with consideration of Ib - if known and/or necessary)

Hi,

"Backwards" refers to the logical way we have to solve this. We KNOW the output values, we don't know the input values yet.
To get the input values we have to work from output to input. The output in this case is the final transistor's emitter current.
"Forward" would refer to what you are talking about, where we know the base current and can follow that through the transistors to get the output.

Simpler example:
We have an input DC voltage source and a resistor from input to output of 100 Ohms and the load is 100 Ohms. This creates a voltage divider.
We are told the output is 5vdc. What is the input?

We have to work 'backwards' to get the input:
Since the voltage divider has two equal resistors and the output voltage is 1/2 of the input, we can calculate that the input must be 2 times the output. Therefore, the input must be 10vdc.
We went from 5v to 10v, not from 10v to 5v. We still had to know the forward transfer ratio, but to get the actual answer we had to figure it as being from output to input which changed the transfer ratio from 1/2 to 2.

 

Hi,
......................
........................
simpler example:
We have an input DC voltage source and a resistor from input to output of 100 Ohms and the load is 100 Ohms. This creates a voltage divider.
We are told the output is 5vdc. What is the input?
We have to work 'backwards' to get the input:
:::::::::::::::::::

I agree, of course, to your example - because: The input DC voltage is the physical cause of the voltage divider output.

However, the situation is somewhat different for the BJT:
Here, the base curent Ib (into the input node of the BJT) is NOT the physical cause, but the RESULT of the biased device.
Instead, the current Ib is just a small part of the emitter current (a kind of unwanted "loss").
(Losses or any other unwanted byproducts are always the result of an electronic function).
But - as I have mentioned at the beginning of my post#13 - the whole thing is not too important, so let`s not further discuss this point (perhaps its only "semanthics").