Bus of Differential Pairs

Thread Starter

mcardoso

Joined May 19, 2020
116
Hi All,

I am very new to PCB routing and was hoping I could get some tips and tricks.

I have a circuit which has 3 differential pairs as inputs (3 channels from an encoder on an industrial robot). The signals contain information based on the relative timing between the channels so it is pretty important that the data arrives in unison.

I have the signals entering the board through screw terminal connectors and landing on a 16-SOIC RS-422 differential receiver. My understanding is that with differential pairs, it is important to keep them tightly coupled (physically near each other) and matched in length. In this application however, do you think it is more important to make all 6 traces the same length at the expense of keeping the traces very tightly coupled?

The length of the run of traces is ~800 mils and the signal is 700kHz max. The installation location is pretty noisy due to nearby SMPS and servo drives.

Here is a picture of my traces where I've traded the shortest path and routing the traces a bit further from each other (especially Channel B in the middle) for length matching all the traces within 1 mil.
1594482719956.png
 

MrChips

Joined Oct 2, 2009
21,377
I would not worry about keeping them the same length. Go for shortest length but keep them paired.
Space the pairs so that ground flood puts a ground between adjacent pairs (not between paired wires).
700kHz would be considered low frequency.
 

andrewmm

Joined Feb 25, 2011
403
You have a few things goign on there.

First the basics.

Differential pairs, by definition are run as a pair, next to each other. Its th einpedance betweent hem you want to keep constant. You select the inpedance by chosing the track size, distance apart and distance above a refereance plane. The plane is normaly constant along the length of th tracks , and is normaly ground.

https://welldoneblog.fedevel.com/2011/08/02/pcb-impedance-calculator-single-ended-differential-pair/

You see you middle of the three trace pairs does not follow this rule.


The thing to remember is why do we have differential pairs ?
We send a signal differentially , by pushing one tracks voltage up whilst pushing the other side down. At the receiver, we subtract one form the other, and receive the difference. The great trick, is that if we have a perfect receiver, and any interference is the same on both the tracks, the the receiver subtracting one form the other, removes all this.

magic.

Thats why we have to run the two traces as a pair, so that anything that happens to one trace happens to the other.
this implies that both tracks of the pair are the same electrical length.

Then we come to the three pairs, and length matching between the pairs.
That comes down to what your application is.

For instance, PCIe runs on differential pairs, 8 GHz region,
But you dont have to match the pairs lengths to each other,

Conversely , I have a DAC chip here, only runs at a few 100 Mhz, but all the pairs have to be length matched.

So without working on your application, then its impossible to say if you have to length match the pairs or not.

One last thing,

As has been implied, now days most differential pairs are used for high speed stuff,

Historically this is not the case, as you have shown.

for instance I've worked on low voltage signals that are run differential just to minimise the pick up. Classic example of that are microphones, and thermo couples, which are much more worried about noise.

https://www.allaboutcircuits.com/technical-articles/the-why-and-how-of-differential-signaling/

Give us a bit more info about your circuit, and we might be able to give a little more help
 

ronsimpson

Joined Oct 7, 2019
726
Matching length of D and /D. Top trace is D and /D with the same length. With a difference in length there is a time where the receiver does not know what to do. The data rate is not the problem. If the length is longer than the response time of the receiver you will likely see noise. During the "?" time the output might be oscillating. The receiver data sheet should give you a good idea of how close the length need to be.
1594507463802.png
About the difference between A, B and C: This will cause the output to arrive early or late. Your circuit may not care. At 700khz it will not matter. I have done this with 800mhz and it is a problem.
 

nsaspook

Joined Aug 27, 2009
7,356
428 meters for a 360 phase shift at 700kHz.
I would not worry about keeping them the same length. Go for shortest length but keep them paired.
Space the pairs so that ground flood puts a ground between adjacent pairs (not between paired wires).
700kHz would be considered low frequency.
The beer mug calculation puts the phase shift at about 0.001 degree per mm difference at 700 kHz signal rate. I think he's safe with the PCB routing.
 

andrewmm

Joined Feb 25, 2011
403
Re the 700 Khz, and length matching,
The period between the transitions is irrelevant,
its the time the signals on the pair are not balanced, and the speed of the receivers. RS422 receivers can run at many 10's of MHz, so you have to balance the pairs electrical length to the speed of the receiver.
 

Thread Starter

mcardoso

Joined May 19, 2020
116
You have a few things goign on there.
Thanks for the detailed reply!

So without working on your application, then its impossible to say if you have to length match the pairs or not.
The application is an industrial encoder attached to a servo motor. The encoder signal output is a 0-700kHz signal based on the speed of the motor. The signals are encoded on RS-422 differential pairs for noise immunity on long cable runs (300' is not unheard of) near noisy equipment.

This specific application is a special encoder that has 3 channels, 2 quadrature tracks (Channels A & B) that encode incremental distance and direction (and speed), and a 3rd channel (Channel D in the image below) that is a pattern based on the other 2 channels which conveys motor commutation and index information.

My specific installation is in an industrial robot with a total cable run of 15-20' in unshielded cables.

B-NOT-A.jpg

Since the information encoded in channel D is based on when the signal rises and falls relative to channels A & B, the timing of the signals at the receiver seems critical to me. One way I am trying to get around glitches caused by trying to sample parallel signals is adding some circuitry around a 2FF synchronizer to discard any data that occurs at a signal transition. So maybe this would fix any issues caused by not length matching the differential pairs. My first circuit didn't have this and I have been getting lots of glitches that I think are caused by metastable input buffering. This is only an issue because multiple signals can change at the same time.

1594586978838.png
 

Thread Starter

mcardoso

Joined May 19, 2020
116
While I am not sure it is important to match the length of all pairs given everyone's comments, I did find a way to route the midle channel to have better coupling and still be the correct length. All 6 traces are within 1 mil of each other

1594589359406.png
 

nsaspook

Joined Aug 27, 2009
7,356
While I am not sure it is important to match the length of all pairs given everyone's comments, I did find a way to route the midle channel to have better coupling and still be the correct length. All 6 traces are within 1 mil of each other

View attachment 212029
Looks fine. At the signal speeds indicated the traces Electrical length is as a practical matter (wrt mechanical variations) are almost zero electromagnetically. If you have glitches it's something other than this IMO.

https://archive.org/details/electromagnetics0000schm/page/8|Page
 

MrChips

Joined Oct 2, 2009
21,377
Why make life difficult?
At 700kHz you can ignore length effects. Just keep them paired and go straight towards your pad connection.

#1 - Eliminate the kink.
#2 - Go the shortest route.
#3 - Looks fine but shift down away from the IC to allow ground pour to get around.
 

MrChips

Joined Oct 2, 2009
21,377
Move the decoupling capacitor C2 to the right so that it is in line with U2 pins on the right.
This will give more space for #3 pair.
 

andrewmm

Joined Feb 25, 2011
403
So we have two parts here, receiving the signals and how you decode the signals.

For receiving, the length variation in the cable over the 100 m length , is far going to far out weigh any matching you do on the PCB. but noise is your enemy, so wire the pairs as short as you can, do not route over any gaps in the ground plane, and all will be well.

The second point, is that you will have a noisy , glitchy , signal just due to the nature of quadrature encoders and the long lines.
you are receiving in a digital circuit by the look of things, , so you can include lots of digital filtering in the digits.

As an example, this code has built in de bounce circuits on the three inputs, that are configurable

https://www.digikey.com/eewiki/pages/viewpage.action?pageId=62259228#QuadratureDecoder(VHDL)-CodeDownload

another example, again with user configurable filters
https://www.cypress.com/file/131871/download
 

Thread Starter

mcardoso

Joined May 19, 2020
116
So we have two parts here, receiving the signals and how you decode the signals.

For receiving, the length variation in the cable over the 100 m length , is far going to far out weigh any matching you do on the PCB. but noise is your enemy, so wire the pairs as short as you can, do not route over any gaps in the ground plane, and all will be well.

The second point, is that you will have a noisy , glitchy , signal just due to the nature of quadrature encoders and the long lines.
you are receiving in a digital circuit by the look of things, , so you can include lots of digital filtering in the digits.

As an example, this code has built in de bounce circuits on the three inputs, that are configurable

https://www.digikey.com/eewiki/pages/viewpage.action?pageId=62259228#QuadratureDecoder(VHDL)-CodeDownload

another example, again with user configurable filters
https://www.cypress.com/file/131871/download
Ah, yeah I guess you are correct. I'm looking to fix the real glitches that occur in my circuit, but it sounds like the cable length matching and differential pair matching really don't contribute substantially to the glitches in the receiving circuit.

I didn't mean to drag this question down to my project specifics level, but it seems to me (based on this and other posts I've made) that project specific information is usually needed to get an appropriate answer since there are so many variables.

Super quick project info: PCB is an interface between proprietary servo motors and non-matching motor drives. Servo manufacturer encoded a lot of data on one wire (Channel D above) using a proprietary ASIC. Their servo drive would have had a matching ASIC to decode the data. I don't have the drive and I can't buy the ASIC, so I am building a PCB to do the same thing. I am not counting the A & B quadrature channels on this board, but rather comparing the Channel D signal to them to decode the data encoded on Channel D. The glitches on the output occur because of metastability - I am synchronizing 3 parallel signals from an asynchronous domain into a clocked domain. I thought that the length matching of the wires might be important to minimize the chances of a glitch. I think the redesigned synchronizer I posted above would solve the length matching and metastability issues by discarding any samples that are taken when inputs are changing value.

Thanks all for the general information on differential pairs as well! Trying to learn as much as I can about PCBs as possible right now.
 

andrewmm

Joined Feb 25, 2011
403
Its probably unlikely what you are seeing is metastabiltiy if the signal is only changing at 700 KHz range.
I'd always double register in an asynchronous signal anyway, as its next to zero impact on the FPGA. Just remember not to reset the first register, then it will be pushed ( probably ) into the FPGA IOB pin .

this gives you the equations to estimate the probability of metastability
http://userweb.eng.gla.ac.uk/scott.roy/DCD3/technotes.pdf

What you will have is a very slow input signal to the RS422 receiver, resulting in the output , even with hysteresis , giving you a bunch of glitches.

If you FPGA is relativly recent, you can use the built in logic analyser capabilities to grab the digital inptu directly to see what you have,.

My betting is when you input is going from say 0 to 1,
your digital input is being sampled as something like

0000001001000010000010001001001010111111111111


What you need is a low pass filter on the inputs,
a de glitch filter.

You will see these on all ( most ) cores that are around,
the same idea is built into processors that have quadrature inputs.

What filter to use, ..
thats a great question, and its a compromise.

The more you filter, the longer the delay you are adding, but the less you filter, the more likely you are to get a glitch.

two easy types of low pass filter.

a) running average, take input, duplicate, inveret and delay one leg, then add the two legs together. The length of the delay determines how many samples you averaging and the number of bits in the accumulator. Set a window comaritor,on way up above a certain vlaue, its a '1', on way down, below a certain vlaue its a '0'

b) pattern detect, when you r output is '0' , wait till you have received say 5 '1' in a row before you declare a '1' . When a your output is '1' , wait till you have 5 '0' in a row, and declare a '0'.

c) up down adder. make a counter, that counts down to '0' and up to 'max' , Counts down 1 hen it receives a 0 , counts up 1 when it receives a 1. Window, so when have a 0 out, wait till counter reaches MAX, to declare a '1'. when have a '1 out, wait till counter reaches zero to declare a '0' out.
 

Thread Starter

mcardoso

Joined May 19, 2020
116
Its probably unlikely what you are seeing is metastabiltiy if the signal is only changing at 700 KHz range.
I'd always double register in an asynchronous signal anyway, as its next to zero impact on the FPGA. Just remember not to reset the first register, then it will be pushed ( probably ) into the FPGA IOB pin .

this gives you the equations to estimate the probability of metastability
http://userweb.eng.gla.ac.uk/scott.roy/DCD3/technotes.pdf

What you will have is a very slow input signal to the RS422 receiver, resulting in the output , even with hysteresis , giving you a bunch of glitches.

If you FPGA is relativly recent, you can use the built in logic analyser capabilities to grab the digital inptu directly to see what you have,.

My betting is when you input is going from say 0 to 1,
your digital input is being sampled as something like

0000001001000010000010001001001010111111111111


What you need is a low pass filter on the inputs,
a de glitch filter.

You will see these on all ( most ) cores that are around,
the same idea is built into processors that have quadrature inputs.

What filter to use, ..
thats a great question, and its a compromise.

The more you filter, the longer the delay you are adding, but the less you filter, the more likely you are to get a glitch.

two easy types of low pass filter.

a) running average, take input, duplicate, inveret and delay one leg, then add the two legs together. The length of the delay determines how many samples you averaging and the number of bits in the accumulator. Set a window comaritor,on way up above a certain vlaue, its a '1', on way down, below a certain vlaue its a '0'

b) pattern detect, when you r output is '0' , wait till you have received say 5 '1' in a row before you declare a '1' . When a your output is '1' , wait till you have 5 '0' in a row, and declare a '0'.

c) up down adder. make a counter, that counts down to '0' and up to 'max' , Counts down 1 hen it receives a 0 , counts up 1 when it receives a 1. Window, so when have a 0 out, wait till counter reaches MAX, to declare a '1'. when have a '1 out, wait till counter reaches zero to declare a '0' out.
So, here's the deal. I'm trying to learn about FPGAs and CPLDs, but I designed my circuit around discrete CMOS logic in the "AC" logic family. It actually works too which surprised the crap out of me. Some people on another forum are helping teach me Xilinx CPLDs for this project which has been awesome, but I don't have a working design yet.

I understand that FPGAs have really short setup and hold times that lend to low probability of metastability. My CMOS D-Type FF has a setup time of 2ns and a hold time of 2ns. The signal frequency is 700kHz and the clock frequency is 8MHz so if I understand the metastability calculations correctly, this calculates to *on average* 22,400 metastable events per second when the motor is running at max speed (one metastable event every 357 clock cycles).

1594660969252.png

Where f_in = 700000, f_clk = 8000000, and t_d = 0.000000004. This is just for one flip flop.

I don't think that the output of the 2FF ever really goes metastable, however my circuit breaks a core rule of sampling asynchronous signals and that is to never sample parallel signals without something like a FIFO in between. Since multiple bits transition at once, it is reasonable to assume they will all go metastable together and resolve before getting to the second flip flop in the synchronizer. Since metastability will resolve to high or low at random, there is a chance the parallel data will be corrupted after the metastability event. I don't have access to the source clock, so I don't see any way to use a more complex method like the asynchronous FIFO.

My circuit modification was to add a XNOR comparison across the first flip flop. If it detects a change in input state, it flips a multiplexer to feedback the 2FF output and basically discard the data. Only when two identical successive samples of the input are detected can the output of the synchronizer update. I think that this should block any corrupted data at the expense of one clock cycle of delay at input transitions. That is what this graphic was trying to show. I think this works sort of like your digital filter you described although maybe there is something better than just a comparing two successive readings without adding a lot of complexity.

1594661760292.png
 

andrewmm

Joined Feb 25, 2011
403
the 2ns set up and hold time is not the number you put into the equation,
the real time a metastable event can occur is the uncertainty window, which is a fraction of that. You will have to pester the chip makers for that info, but you would be lucky.

The reason is that given that 2ns, at any given voltage temperature , process node, a signal that changes at say 1.5 ns before will still meet setup, as would a signal that changes at say 0.5ns, The real number is going to be pico seconds at most,

Using logic instead of a FPGA CPLD, is a very hard way to work.
A FPGA you can simulate, and prove the function. The hard wired logic, you have 1001 other factors to account for, for PSU to tracking, pickup et all,

Your decoder is going to be effectively a state machine, and as you have seen, the machine can get large,
its much easier to simulate and debug a state machine in an FPGA.


Look at these sort of thing

https://shop.trenz-electronic.de/en/27383-Cmod-A7-Breadboardable-Artix-7-15T-FPGA-Module
 

Thread Starter

mcardoso

Joined May 19, 2020
116
Thanks again for the feedback.

I have a lot to learn about metastability (thought I understood it!). I hope I did correctly diagnose my glitches as being part of the input circuitry and not something else I have not yet considered.

I wish I had started with a FPGA or CPLD. This project seemed simple enough that it didn't warrant trying to learn FPGAs from scratch, but at this point the effort probably would have been a wash and the flexibility of the FPGA would have been great! I don't regret the efforts I have made thus far since I have learned a ton about CMOS, synchronous circuit design, oscillators, flip-flops, etc. which I never would have picked up otherwise.

I bought parts to try a Version 2.0 of my original circuit (including some DIP versions of my components to breadboard and rework the existing board). If I cannot get the reworked board to function, then I might need to ditch the CMOS logic all together and start over with a CPLD/FPGA.
 

Thread Starter

mcardoso

Joined May 19, 2020
116
Wanted to post an update to the couple of threads I had started related to this circuit. I updated my design to include the circuit modification and discussed above. This involved adding (1) 4 Channel 2-Input XNOR gate, (1) 3 Channel 3-Input AND gate, and (1) 4 Channel 2:1 multiplexer. These chips work together to detect when an input has changed state and prevent that sample from entering the circuit. Only when 2 successive input readings agree can the outputs of the circuit be updated.

The circuit still functions with the changes I made and all the glitches seem to be gone! I really appreciate all the help and feedback from everyone here.
 
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