Hi all!

Im working on this exercise, I have this sequential circuit and I have to complete the timetable.
Here I attached the sequential circuit and my timetable (black lines are given by the exercise, blue lines are my work by the moment).
The verification tool says it's not correct but doesn't give a clue why.

Here are my reasons by the moment:
- I think e1 signal is correct (maybe Im wrong), I think it just get 0 value at t3
- Im not sure about e2 but I think it values 1 at some point in the blank space I have to fill in, so it makes D value 0 and then makes D get value 1 again.
- s and nQ values are always opposite since nQ is NOT s
- At the beginning e2 is 1, so "s" should value 0 since e2 is a Reset signal that puts the bi-stable to 0.
- Since "s" values 0, nQ should value 1
- And from the last two points, D should value 1 since the XOR is receiving 0 1 = 1
From here I think my blank spaces (blue lines) are correct but obviously they're not.
Im pretty sure about D, s and nQ values but Im not sure about e1 and e2, only thing I see is that reset signal is sending 1 again at some point between t2 and t3

Any help, clue, explanation or thoughts will be very appreciated.

 

- s and nQ values are always opposite since nQ is NOT s

If S=1 then the 'D' type would be set (Q=1, nQ=0), but while S=0 it has no effect on the outputs. They can be changed by the Reset or D/Clock.

 

At the first rising clock edge what is the value of D? So what should the value of s be just after the first rising clock edge?

EDIT: I didn't notice that the reset is asserted at this time.

 

Hi all!

Im working on this exercise, I have this sequential circuit and I have to complete the timetable.
Here I attached the sequential circuit and my timetable (black lines are given by the exercise, blue lines are my work by the moment).
The verification tool says it's not correct but doesn't give a clue why.

Here are my reasons by the moment:
- I think e1 signal is correct (maybe Im wrong), I think it just get 0 value at t3
- Im not sure about e2 but I think it values 1 at some point in the blank space I have to fill in, so it makes D value 0 and then makes D get value 1 again.
- s and nQ values are always opposite since nQ is NOT s
- At the beginning e2 is 1, so "s" should value 0 since e2 is a Reset signal that puts the bi-stable to 0.
- Since "s" values 0, nQ should value 1
- And from the last two points, D should value 1 since the XOR is receiving 0 1 = 1
From here I think my blank spaces (blue lines) are correct but obviously they're not.
Im pretty sure about D, s and nQ values but Im not sure about e1 and e2, only thing I see is that reset signal is sending 1 again at some point between t2 and t3

Any help, clue, explanation or thoughts will be very appreciated.
View attachment 116046 View attachment 116047

Hi,

This seems like an unusual question for a logic type problem. For example, e1 and e2 are external stimuli and so would normally be part of the question not part of he answer, unless you are just required to show one example that you make up yourself. That's because there is no good reason for e2 to change in the middle there, and even though e1 does have to come back low again at some point there's no reason why it has to stay high for a longer time or for a shorter time. Is it that you are allowed to make up your own examples?
In other words, how do we know if e1 is to go low at t2 or at t3 unless we can make that up ourselves? Could it also be that we have to show BOTH possibilities?
Note that the clock signal is shown in it's entirety and that's another external stimulus.

 

It's not that unusual -- you are given part of the information and tasked with determining what the missing pieces need to be.

For instance, at the second rising clock edge Nq has fallen LO and e1 is still LO. So what should D now be?

There are ranges of times during which a signal could change, so just pick a point in time around the midpoint.

 

At the first rising clock edge what is the value of D? So what should the value of s be just after the first rising clock edge?

EDIT: I didn't notice that the reset is asserted at this time.

Hi,

By reset is asserted, I guess u mean its value is 1. So, if Im not wrong, while the reset signal is 1 the flip flop value is 0, so s=0, so nQ=1 and the XOR door is receiving at the moment 01 = 1 so D=1.

Am I right?

 

If S=1 then the 'D' type would be set (Q=1, nQ=0), but while S=0 it has no effect on the outputs. They can be changed by the Reset or D/Clock.

Hi,

Im not sure I get it, I thought that while the RESET signal is 1 the flip flop value is 0 (s=0). I don't understand what you mean "while S=0 has no effect on the outputs, they can be changed by the Rest or D/clock"

I modified the table based on WBahn advise and now I see D changes based on nQ value change at first rising clock and then change again just a little bit later based on e1 change value to 1.

 

I don't understand what you mean "while S=0 has no effect on the outputs, they can be changed by the Rest or D/clock"

Ah, sorry for confusing you even more. There are two esses on the diagram, s and S. You were referring to s and I was referring to S.

 

Hi guys,

By the moment I have this timing diagram, by fixing D (I think I fixed it). Just give me a clue about if D, s and nQ are correct because I still don't know what to do with e1 and e2 blank spaces.

I think e2 is wrong in my first timing table, because if it values 1, then s should value 0 and it is not like that, at that point the given table says s=1, so e2 should be 0 all the blank space.

I think I have it correct now, Im gonna upload it so you can just tell me if it's correct or not to keep working on this.