I need to build an electronic light dimmer for my Logic Design class. We are given a state table and told to build the circuit using JK Flip Flops. We are suppose to build the JK Flip Flop using 2 2 to 1 multiplexers. So far I've only be able to implement a JK FF using 3 2 to 1 MUXs. Is it possible to implement this using 2 2 to 1 MUXs?

 

Are there any other requirements to your problem? Is it that you can only use 2 2x1 multiplexers, or can you use basic logic gates as well?

I will try to work it out when I get a chance later today.

 

you can use the enable input of the multiplexer as an input.(if u are having a problem with the i/p terminals limitation)

 

We can use anything in our lab kit to build it. We have quad input AND,OR,NAND,NOR,XOR gates as well as other ICs such as counters. This lab forces to use a multiplexer because it would be far too complicated to build a JK FF with gates (and I don't have enough gates). I'm not sure who I can implement the JK using the enable as an input. I have worked out how I can build the circuit with a 4 to 1 MUX (except the clock input). After that, I realized that I only had 2 to 1 MUX to use. I figured out how to do it using a 3 2 to 1 MUX. (Table is hard to see, the | seperate the columns)
|MUX1: | MUX2: | MUX3
0 |Q | 0 | Output of MUX1
1 |1 | Q' | Output of MUX2
Enable |J | J | K

If I had a 4 to 1 MUX, I could do it like this

JK Q+
00 Q
01 0
10 1
11 Q'

Where Q is the present state and Q+ is the next state. Is there a simple way using logic gates to do this without building another MUX from gates? Thanks for the help. Also, If recca2 could write up how I should wire up the 2 MUXs to implement the JK FF in some sort of table that would really help.

 

I checked the lab manual and the experiment worksheet we are given and we are suppose to use 4 4 to 1 MUXs. My question is, why does it take 2 4 to 1 MUX to implement a JK flip flop? Each MUX handles a different variable. Like J1 would have a MUX, K1 has a MUX, J2 has a MUX, and K2 has a MUX. The only thing I can think of is that one input is for the variable (J or K) and the other input is for the clock. Is this correct? In this case, how would I have to wire the MUXs together to implement a JK flip flop?

 

perhaps a schematic (rough one will do) might be able to help.
i m not sure we can build a clocked FF using only two 2:1 mux.
hopefully someone with more experience here might be able to help you further.