Hi,
I have a question regarding Buck regulator output capacitors via current sharing.
we have 12V to 1V @ 35A regulator design, which uses 7x100uF,5x150uF bulk capacitors, which are placed sequentially few on TOP and remaining are ON BOT layers with vias connecting all capacitors from TOP to BOT and Internal shape which carries the current to load.
When we have simulated IR drop, Plane drop, power density, via current density using POWER DC we see most of the current is handled by via which is very close to first Output capacitor . Actually all vias should share the current equally to internal planes.
Is this the real scenario, whether all the vias in the output power plane won't share current equally.
If we need to share current equally, what needs to be done. I see in Evaluation board layout the via's are arranged very symmetrically with equal vertical & Horizontal spacings - maintaining such a symmetry is required?
I have our report for reference and Vendor EVB reference layout for comparison.
I don't know whether i clearly explained my scenario.
Here, are my questions.
1. In regulators layout's Output capacitors will be arranged sequentially few on TOP and few on BOTTOM layers. The ripple current shared by these capacitors whether varies based on Capacitor relative position from Inductor, How much will be the ripple share between TOP & BOTTOM side capacitors.
2. Whether BOTTOM capacitors will conduct any ripple current compared to TOP capacitors.
3. We have output shape starting from Inductor to some distance to connect all Output capacitors on TOP & BOT. This shape has via's which are used to share current between TOP to Internal Power planes. Whether these via's needs to have symmetry to share current equally .
I have a question regarding Buck regulator output capacitors via current sharing.
we have 12V to 1V @ 35A regulator design, which uses 7x100uF,5x150uF bulk capacitors, which are placed sequentially few on TOP and remaining are ON BOT layers with vias connecting all capacitors from TOP to BOT and Internal shape which carries the current to load.
When we have simulated IR drop, Plane drop, power density, via current density using POWER DC we see most of the current is handled by via which is very close to first Output capacitor . Actually all vias should share the current equally to internal planes.
Is this the real scenario, whether all the vias in the output power plane won't share current equally.
If we need to share current equally, what needs to be done. I see in Evaluation board layout the via's are arranged very symmetrically with equal vertical & Horizontal spacings - maintaining such a symmetry is required?
I have our report for reference and Vendor EVB reference layout for comparison.
I don't know whether i clearly explained my scenario.
Here, are my questions.
1. In regulators layout's Output capacitors will be arranged sequentially few on TOP and few on BOTTOM layers. The ripple current shared by these capacitors whether varies based on Capacitor relative position from Inductor, How much will be the ripple share between TOP & BOTTOM side capacitors.
2. Whether BOTTOM capacitors will conduct any ripple current compared to TOP capacitors.
3. We have output shape starting from Inductor to some distance to connect all Output capacitors on TOP & BOT. This shape has via's which are used to share current between TOP to Internal Power planes. Whether these via's needs to have symmetry to share current equally .
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