Buck regulator output capacitor via current sharing

Thread Starter

malli_1729

Joined Nov 28, 2012
26
Hi,

I have a question regarding Buck regulator output capacitors via current sharing.
we have 12V to 1V @ 35A regulator design, which uses 7x100uF,5x150uF bulk capacitors, which are placed sequentially few on TOP and remaining are ON BOT layers with vias connecting all capacitors from TOP to BOT and Internal shape which carries the current to load.
When we have simulated IR drop, Plane drop, power density, via current density using POWER DC we see most of the current is handled by via which is very close to first Output capacitor . Actually all vias should share the current equally to internal planes.

Is this the real scenario, whether all the vias in the output power plane won't share current equally.
If we need to share current equally, what needs to be done. I see in Evaluation board layout the via's are arranged very symmetrically with equal vertical & Horizontal spacings - maintaining such a symmetry is required?

I have our report for reference and Vendor EVB reference layout for comparison.

I don't know whether i clearly explained my scenario.
Here, are my questions.
1. In regulators layout's Output capacitors will be arranged sequentially few on TOP and few on BOTTOM layers. The ripple current shared by these capacitors whether varies based on Capacitor relative position from Inductor, How much will be the ripple share between TOP & BOTTOM side capacitors.
2. Whether BOTTOM capacitors will conduct any ripple current compared to TOP capacitors.
3. We have output shape starting from Inductor to some distance to connect all Output capacitors on TOP & BOT. This shape has via's which are used to share current between TOP to Internal Power planes. Whether these via's needs to have symmetry to share current equally .
 

Attachments

Last edited:

andrewmm

Joined Feb 25, 2011
909
basically,
follow the evaluation board, and any notes in the data sheet / app notes.

Vias and tracks can be very inductive,
which when hit by the high current, fast transients of the buck , are very significant.

The "stripline" type effect of these high speed / high current pulses cause the board to be significant in the design.

Break what the manufacturers say at your risk,
 

Delta prime

Joined Nov 15, 2019
617
Hello there
:)
I see in Evaluation board layout the vias are arranged very symmetrically with equal veritical & Horizontal spacings - maintaining such a symmetry is required?
Absolutely, with all the data you have amassed
It's only mattered time for your aha! moment,
And that's a pretty good evaluation board if I do say so myself I have designed & still do design buck converters that can handle up to 56A for a single output,
the I squared R, DC losses at 56A can increase greatly due to the higher resistance of the copper-poured area. the copper-poured area, via size and quantity, and current loop path on a multi-layer circuit board.
PCB layout is crucial in regards to heat dissipation and efficiency.
Just like the flat copper area and thickness, vias have a finite resistance. So you must optimize the vias’ quantity and size to optimize the thermal performance and efficiency of a converter design.Vias make up series-resistance elements when they connect two traces or plane together. Generally, multiple vias in parallel along with symmetry of the vias will reduce the effective resistance.
;)
 
Last edited:

Thread Starter

malli_1729

Joined Nov 28, 2012
26
Hello there
:)
Absolutely, with all the data you have amassed
It's only mattered time for your aha! moment,
And that's a pretty good evaluation board if I do say so myself I have designed & still do design buck converters that can handle up to 56A for a single output,
the I squared R, DC losses at 56A can increase greatly due to the higher resistance of the copper-poured area. the copper-poured area, via size and quantity, and current loop path on a multi-layer circuit board.
PCB layout is crucial in regards to heat dissipation and efficiency.
Just like the flat copper area and thickness, vias have a finite resistance. So you must optimize the vias’ quantity and size to optimize the thermal performance and efficiency of a converter design.Vias make up series-resistance elements when they connect two traces or plane together. Generally, multiple vias in parallel along with symmetry of the vias will reduce the effective resistance.
;)
These are general considerations, What i am asking is in the EVB every bulk capacitor has 3 vias kept very close and in symmetry, In our case we use vias randomly not in symmetrical way, Because we are not following symmetry maximum current is passing through first via near first bulk capacitor.
Is this symmetry required.
 

Delta prime

Joined Nov 15, 2019
617
Yes I am speaking in generalities, any design engineer worth his weight in salt would have a schematic a bom, component placement diagram, and you're still months away from production.
Have a look at this.
Tell me what you think.
:)
 

Attachments

kaindub

Joined Oct 28, 2019
45
Remember that current follows the path of least resistance.
A couple of suggestions
Dont use vias. Due to the small plating thickness the vias are a high resistance connection. Better to install vias that are 0.8mm and solder in a wire to carry the current. (ie Use through hole links)
Place the 100uF capacitors closer to the chip than the 150uF caps. The smaller caps have less impedance and would draw less current allowing better current sharing.
Why do you have different size caps? The filter cap value seems rather large.
Increase the switching frequency.
Increase the inductor value
Decrease the input voltage.
Place all caps on one side of the board and use as heavy a copper as you can.
 

Thread Starter

malli_1729

Joined Nov 28, 2012
26
Yes I am speaking in generalities, any design engineer worth his weight in salt would have a schematic a bom, component placement diagram, and you're still months away from production.
Have a look at this.
Tell me what you think.
:)
Hi Delta,

I have seen this app note. thanks.
in this app note, i see information on buck regulator layout Cin placement,SW node copper,FB routing etc, don't see any information on via current sharing, via symmetry data.
I don't see any quantitative analysis on these kind of things from app notes.
 

Thread Starter

malli_1729

Joined Nov 28, 2012
26
Remember that current follows the path of least resistance.
A couple of suggestions
Dont use vias. Due to the small plating thickness the vias are a high resistance connection. Better to install vias that are 0.8mm and solder in a wire to carry the current. (ie Use through hole links)
-- soldering a wire is not possible in our boards.
Place the 100uF capacitors closer to the chip than the 150uF caps. The smaller caps have less impedance and would draw less current allowing better current sharing.
Why do you have different size caps? The filter cap value seems rather large.
-- These designs are older designs, these capacitor values are fine because of transient requirements on ASIC side.
Increase the switching frequency.
Increase the inductor value
Decrease the input voltage.
Place all caps on one side of the board and use as heavy a copper as you can.
-- WE can't keep all capacitors on One side , not possible due to space constraints
 

andrewmm

Joined Feb 25, 2011
909
@malli_1729

As you have now seen, the placement of power supply capacitors and track routing is very "variable"
some "right" designed boards have failed, and many wrong designed board have passed most of the time.

what ever right and wrong is.

Its all very personal.

Follow the data sheet / evaluation board as best you can is the best advise I can give,

no matter what you do , it will probably work ,
its just how much risk you want to take,

The touch stone I use, is
"in a court of law, could I justify my choices"
 

ronsimpson

Joined Oct 7, 2019
1,125
I can not see all the layers and can not see why the current passes through some VIAs more than others. You have good wide copper and many VIAs. With out seeing the other layers I can not know why current is flowing the way it seems to flow.

Are you measuring the temperature of the board to get current? I want a lot more information on how this works. Why do you think three VIAs are taking all the current.
 
Last edited:

WBahn

Joined Mar 31, 2012
26,398
Whether these via's needs to have symmetry to share current equally .
In general the answer will be that if they are symmetrical (using whatever you mean by the term) then they probably won't share the current equally. That's because the parts of the circuit, including parasitics, will likely not be symmetrical and so if you really want the vias to share the current equally you have to lay them out in a non-symmetrical way to compensate for the net effect of all the other asymmetries.

What you really want to focus on is whether they will share current equally enough in order to meet your needs. This, in turn, means that you need to define pretty clearly what will constitute sharing current equally enough. If it is really a concern, you will likely then have to model the parasitics well enough to answer the question, which can be an adventure in and of itself just to determine what constitutes having modeled them well enough.
 
Top