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Hello guys,
I am new in here.
I was thinking of ways to reduce the cost for buck converter. Most of the textbooks talk about NMOS on the top side. Advantages of using an NMOS would be its lower Rds(on) and easy availability. But if we use an NMOS on top side, we must have a separate gate driver IC , as gating signal has to with respect to source(also if difference between voltage Source and load voltage are not significantly large, we will be forced to use synchronous buck configuration). All these factors make the buck converter costly.
To reduce cost, one way is to place NMOS in the ground rail between the negative terminals of source and load as shown in attachment 1. This is acceptable for simple buck converters which run in open loop and at lower voltages. But if we have a closed loop system when we measure load voltage and source voltage and drive the mosfet based on these parameters, this configuration will fail( because reference point is not same). Also I don't think it is very safe.
21Tlb.png
The solution to this would be using a PMOS on top side. P channel power mosfets ( like IRF95x0 series) have slightly higher Rds on than corresponding N channel mosfets. Rds will only change power loss and will not cause any problem to the functioning of the device. The real issue with PMOS is its Vgs. You can refer to this thread for knowing how Vgs constraint affects the design
https://forum.allaboutcircuits.com/threads/high-voltage-buck-converter.62817/
If my voltage source is 100V and load is 12V, Vds will be 88V which is lower than the Vds limit of IRF series P-Mosfets. Threshold voltage is -4V .
But max |Vgs| that can be applied is 20V. That is, if I want to make the PMOS conducting, I have to apply any voltage between -4V to -20V across source and gate terminals.
In a buck converter the source of mosfet is connected to positive terminal of the voltage source. To make it stop conducting, the gate should get high voltage of above 97V ( with ground as reference). This can be easily done using BJTs. But the real problem comes when we are trying to make it conduct. -4V to -20V Vgs implies 96 to 80V at gate (with reference to ground). We can use resistor dividers to get this voltage but then, high frequency applications demand larger current at the instant of turning mosfet ON which cannot be supplied if we are using resistor dividers.
I came up with a circuit to limit Vgs to -10V when source is at 100V. Here I have used a capacitor divider inside totempole configuration. The input is 3.3V level and is at 100KHz frequency. Simulation works fine on LTSpice. Also i have attached the waveform of Vgs
Can you please verify the circuit and comment any issues that i might face when I make this circuit on PCB.
Sorry for the messy circuit and my grammar.
Thanks in Advance
I am new in here.
I was thinking of ways to reduce the cost for buck converter. Most of the textbooks talk about NMOS on the top side. Advantages of using an NMOS would be its lower Rds(on) and easy availability. But if we use an NMOS on top side, we must have a separate gate driver IC , as gating signal has to with respect to source(also if difference between voltage Source and load voltage are not significantly large, we will be forced to use synchronous buck configuration). All these factors make the buck converter costly.
To reduce cost, one way is to place NMOS in the ground rail between the negative terminals of source and load as shown in attachment 1. This is acceptable for simple buck converters which run in open loop and at lower voltages. But if we have a closed loop system when we measure load voltage and source voltage and drive the mosfet based on these parameters, this configuration will fail( because reference point is not same). Also I don't think it is very safe.
21Tlb.png
The solution to this would be using a PMOS on top side. P channel power mosfets ( like IRF95x0 series) have slightly higher Rds on than corresponding N channel mosfets. Rds will only change power loss and will not cause any problem to the functioning of the device. The real issue with PMOS is its Vgs. You can refer to this thread for knowing how Vgs constraint affects the design
https://forum.allaboutcircuits.com/threads/high-voltage-buck-converter.62817/
If my voltage source is 100V and load is 12V, Vds will be 88V which is lower than the Vds limit of IRF series P-Mosfets. Threshold voltage is -4V .
But max |Vgs| that can be applied is 20V. That is, if I want to make the PMOS conducting, I have to apply any voltage between -4V to -20V across source and gate terminals.
In a buck converter the source of mosfet is connected to positive terminal of the voltage source. To make it stop conducting, the gate should get high voltage of above 97V ( with ground as reference). This can be easily done using BJTs. But the real problem comes when we are trying to make it conduct. -4V to -20V Vgs implies 96 to 80V at gate (with reference to ground). We can use resistor dividers to get this voltage but then, high frequency applications demand larger current at the instant of turning mosfet ON which cannot be supplied if we are using resistor dividers.
I came up with a circuit to limit Vgs to -10V when source is at 100V. Here I have used a capacitor divider inside totempole configuration. The input is 3.3V level and is at 100KHz frequency. Simulation works fine on LTSpice. Also i have attached the waveform of Vgs
Can you please verify the circuit and comment any issues that i might face when I make this circuit on PCB.
Sorry for the messy circuit and my grammar.
Thanks in Advance
