Hi everyone
I need some help about bjt distortion.
I don't understand why this situation is happened.
Please look at this circuit and simulations


The first one is my circuit and the second one is about RL = 100k
But i want to know the last situation RL = 100



I think that there is no dc bias change
Because in dc analysis we change capacitor in short circuit right? So we only change RL there is no dc bias change
But there is a distortion...
Please help me.. my head was broken..

 

The first output has distortion due to the large-signal non-linearity of Q2.
(Small-signal is when the stage is operating with a signal current much smaller than the bias current, where the transistor can be assumed to be linear.
Large-signal is when the stage operates with the signal current being a large percentage of the bias current and the transistor is no longer linear).
You can reduce this non-linearity distortion (at the expense of gain) by placing a resistor in series with C6 (which adds some negative feedback).
The gain will be approximately R7 / (added resistor value).
How much gain do you need?

The second has much more distortion due to the large-signal output impedance of an emitter follower being much lower for a positive going signal, than a negative going one.
You have to be aware that the large signal impedance of this circuit is much different than the small signal impedance.
For a negative going large-signal, all the load current must be sunk by R11 since Q3 cannot provide any negative current.
Since R11 is much larger than the 100 ohm load, the bottom of the signal is severely truncated.

If you monitor the circuit currents in your simulation you will see what is happening.

This is why a push-pull output stage is typically used to drive a low-impedance load.

 

The first output has distortion due to the large-signal non-linearity of Q2.
(Small-signal is when the stage is operating with a signal current much smaller than the bias current, where the transistor can be assumed to be linear.
Large-signal is when the stage operates with the signal current being a large percentage of the bias current and the transistor is no longer linear).
You can reduce this non-linearity distortion (at the expense of gain) by placing a resistor in series with C6 (which adds some negative feedback).
The gain will be approximately R7 / (added resistor value).
How much gain do you need?

The second has much more distortion due to the large-signal output impedance of an emitter follower being much lower for a positive going signal, than a negative going one.
You have to be aware that the large signal impedance of this circuit is much different than the small signal impedance.
For a negative going large-signal, all the load current must be sunk by R11 since Q3 cannot provide any negative current.
Since R11 is much larger than the 100 ohm load, the bottom of the signal is severely truncated.

If you monitor the circuit currents in your simulation you will see what is happening.

This is why a push-pull output stage is typically used to drive a low-impedance load.

Thank you for your help!
Umm..
Because of large signal (not small signal), current by large signal affect bias condition?
Negative signal do not generate ic that we want to make? I cant understand exactly....

 

Because of large signal (not small signal), current by large signal affect bias condition?

It doesn't affect the average bias current.
But the large change in the bias current with signal means that the gain and Vbe of the transistor change with the instantaneous change in signal level.
That's what causes the distortion of the first stage.

Negative signal do not generate ic that we want to make? I cant understand exactly....

And I don't exactly understand your question.
What is "ic"?.

The problem is that to generate a peak negative voltage at the output equal to the positive peak, the negative current has to be provided by R11.
If the required current is greater than what R11 can sink to ground, then the output will be distorted.
For example, your plot shows a peak output signal of about 650mV into the 100Ω load, which requires a current of .65/100 = 6.5mA.
Thus for a 650mV negative peak, the current through R11 must be >6.5mA.
But this requires a voltage drop across R11 of 6.5mA * 2k =13V which is much greater than the bias voltage at Q3's emitter.

If you reduce the value of R11 to < (Vbias-Vp)/6.5mA where Vbias is the DC emitter bias voltage at Q3 and Vp is the peak output AC voltage, then the output negative peak will not be significantly truncated.

Have you looked at the circuit currents as I suggested?

 

It doesn't affect the average bias current.
But the large change in the bias current with signal means that the gain and Vbe of the transistor change with the instantaneous change in signal level.
That's what causes the distortion of the first stage.
And I don't exactly understand your question.
What is "ic"?.

The problem is that to generate a peak negative voltage at the output equal to the positive peak, the negative current has to be provided by R11.
If the required current is greater than what R11 can sink to ground, then the output will be distorted.
For example, your plot shows a peak output signal of about 650mV into the 100Ω load, which requires a current of .65/100 = 6.5mA.
Thus for a 650mV negative peak, the current through R11 must be >6.5mA.
But this requires a voltage drop across R11 of 6.5mA * 2k =13V which is much greater than the bias voltage at Q3's emitter.

If you reduce the value of R11 to < (Vbias-Vp)/6.5mA where Vbias is the DC emitter bias voltage at Q3 and Vp is the peak output AC voltage, then the output negative peak will not be significantly truncated.

Have you looked at the circuit currents as I suggested?

Yes i have looked this currents graph at emitter.
umm..
emitter current must not be over + sign, so there is distortion??

 

emitter current must not be over + sign, so there is distortion??

The emitter current cannot go below zero obviously (transistor is fully off), so at that point the output is clipped.

 

See how the nonlinear distortion depends on the amplitude of the input signal