Beginner Problem in VHDL

Thread Starter

MDS

Joined Nov 19, 2009
1
Hello Everybody,
I'm a beginner in VHDL and I hope you can help me.I have 3 files.Testbench of a 16bit counter and a clkAndReset generator and a 16 bit counter. I have to use the generated clock and reset in the clkAndReset file in counter but I don't know how to do this.
Here are my three files :

Testbench :
Rich (BB code):
library ieee;
use ieee.std_logic_1164.all;

entity testbench_synchroner_zaehler is
  --leer
end testbench_synchroner_zaehler;

architecture bhv of testbench_synchroner_zaehler is
component clkAndReset is
     generic (T : time := 20 ns);
     port (
       -- TAKT SIGNAL
       clk     : out std_logic;
       -- RESET SIGNAL
       reset   : out std_logic;
       
       SIM_end : in std_logic
       );
   end component;
   
   component zaehler is
port (
  clk_Z : in std_logic;
  reset_Z : in std_logic;
  Q_Z : OUT std_logic_vector(15 downto 0));
end component;
   
   signal clk1 : std_logic;
   signal reset1 : std_logic;
   signal sim_end1 : std_logic;
   signal Q1 : std_logic_vector(15 downto 0);
   
   begin
       reset1<='0';
       sim_end1<='0';       
       
      u2 : zaehler port map(clk1,reset1,q1); 
      u1 : clkAndReset port map(clk1,reset1,sim_end1);
    end bhv;
ClkAndReset:
Rich (BB code):
library ieee;
use ieee.std_logic_1164.all;

-- ----------------------------------------------------------------------------
-- entity                                                                    --
-- ----------------------------------------------------------------------------
entity clkAndReset is
  generic (T : time := 20 ns);
  port (
    -- TAKT SIGNAL
    clk     : out std_logic;
    -- RESET SIGNAL
    reset   : out std_logic;
    
    SIM_end : in std_logic
    );
end clkAndReset;

-- ----------------------------------------------------------------------------
-- architecture                                                              --
-- ----------------------------------------------------------------------------
architecture clk of clkAndReset is
  signal counter: integer:=0;
  begin
      process
          begin
              if SIM_end = '1' then
                  clk <= '0';
                  wait;
            else
               counter<=counter+1;
               clk<='0';
               wait for T/2;
               clk<='1';
               wait for T/2;
               if counter>4 then
                   reset<='1';
                   else
                   reset<='0';
            end if;
           end if;
       end process;
end architecture;
Counter :
Rich (BB code):
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity zaehler is
port (
  clk_z : in std_logic;
  reset_z : in std_logic;
  --SIM_end : in std_logic;
  Q_z : OUT std_logic_vector(15 downto 0));
end zaehler;

architecture behavior of zaehler is
  
  signal clk1 : std_logic;
  signal reset1 : std_logic;
  signal counter:std_logic_vector(15 downto 0);

  begin
      process
        begin
          if reset_z = '1' then
          counter<="0000000000000000";
          Q_z <= counter;
        end if;
        if (clk_zlibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity zaehler is
port (
  clk_z : in std_logic;
  reset_z : in std_logic;
  --SIM_end : in std_logic;
  Q_z : OUT std_logic_vector(15 downto 0));
end zaehler;

architecture behavior of zaehler is
  
  signal clk1 : std_logic;
  signal reset1 : std_logic;
  signal counter:std_logic_vector(15 downto 0);

  begin
      process
        begin
          if reset_z = '1' then
          counter<="0000000000000000";
          Q_z <= counter;
        end if;
        if (clk_z = '1') then
          counter <= counter+'1';
          Q_z<=counter;
      end if;
  end process;
  
end behavior;
 = '1') then
          counter <= counter+'1';
          Q_z<=counter;
      end if;
  end process;
  
end behavior;

I think that the counter and clkAndReset working properly and the problem is that i can't pass the clk and reset from clkAndReset to counter.
What do you think??
 
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