hi guyes ..
i am new to vhdl and i tried to write code for serial to parallel converter but it doesn't perform well .. that is the code but b4 u read it, let me explain my idea so that you get the idea quickly ..
it is 4 bit S/P .. i used DeMUX with selection bits incremented each clock so that each input bit is stored in the signal called s. after the selection reaches "11" meaning the 4 bits have been completely appeared on the signal s, then i let the output pins (dout) carry the content of the signal s ..
please if anybody can help fix the bug in my code ..
by the way, i am using FPGAdvantage by Mentor Grphx ..
thx in advance ..
i am new to vhdl and i tried to write code for serial to parallel converter but it doesn't perform well .. that is the code but b4 u read it, let me explain my idea so that you get the idea quickly ..
it is 4 bit S/P .. i used DeMUX with selection bits incremented each clock so that each input bit is stored in the signal called s. after the selection reaches "11" meaning the 4 bits have been completely appeared on the signal s, then i let the output pins (dout) carry the content of the signal s ..
please if anybody can help fix the bug in my code ..
by the way, i am using FPGAdvantage by Mentor Grphx ..
thx in advance ..
Rich (BB code):
--
-- VHDL Architecture AHMED_lib.Parallel_Serial_DeMUX.Behave
--
-- Created:
-- by - Ahmed.UNKNOWN (AHMED-PC)
-- at - 22:04:50 09/17/2009
--
-- using Mentor Graphics HDL Designer(TM) 2005.3 (Build 75)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY Parallel_Serial_DeMUX IS
port (din: in std_logic;
dout: out std_logic_vector (3 downto 0);
clk,rst: in std_logic);
END ENTITY Parallel_Serial_DeMUX;
--
ARCHITECTURE Behave OF Parallel_Serial_DeMUX IS
signal s: std_logic_vector (3 downto 0):="0000";
signal sel: std_logic_vector (1 downto 0):="00";
BEGIN
process (clk,rst)
begin
if clk'event and clk='1' then
if rst='0' then
s(conv_integer(sel))<=din;
CASE sel is
WHEN "11" =>
dout<=s;
dout(3)<=s(3);
sel <="00";
s<="0000";
WHEN others =>
sel<=sel+"01";
END CASE;
else
dout<="0000";
s<="0000";
end if;
end if;
end process;
END ARCHITECTURE Behave;