which resistor do you need to put it into this DC point?

The 47k resistor. Re-read post #17.
Since this is a CMOS inverter its input current is virtually zero and its output impedance is much lower than 47K. Knowing those facts, since this is Homework I leave it to you to calculate the theoretical gain.

 

The 47k resistor. Re-read post #17.
Since this is a CMOS inverter its input current is virtually zero and its output impedance is much lower than 47K. Knowing those facts, since this is Homework I leave it to you to calculate the theoretical gain.

Hello,

It is not a homework (I encontered this in an older design) but I asked to a senior electronics where I work and he couldn´t help me because he is more like an analog guy. It put the post in Homework because I think it is something "easy" and more fittable in here. Thanks to your comments give me a clue on how to calculate this gain but still a little bit lost about how to obtain the value of 47K resistor. I hope there are not silly questions to you or bother you in any way. I´m the kind of person that likes to know how to do stuff and how they really works before taking them from granted. I asked them in here after making a research myself before and not to be able to find an answer to this alone.

Sorry for the long response. And really thank you for your time.

 

Mmmmmm, so how can you calculate the gain and which resistor do you need to put it into this DC point?

The question is why you would want to? CMOS gates should never be operated in between the off and on states. They basically look like a short circuit when the input is somewhere in the middle because both transistors are on.

 

The question is why you would want to? CMOS gates should never be operated in between the off and on states. They basically look like a short circuit when the input is somewhere in the middle because both transistors are on.

I don't want to use this specific structure for any reason. They made me used it because they already have it implemented in other product. I have to put it in my desing and I don't want to let something there that I don't really fully undestand.

 

Take the resistor out and see what happens. I think you will find a better signal at the output.

Did the previous circuit use the same logic family? Perhaps it was needed for reasons that no longer apply.

 

how to obtain the value of 47K resistor.

It is fairly arbitrary. Even 470k or so would probably work, but might make the gate operation sensitive to noise pick-up.

 

RCA Semiconductor had an app note which described in wonderful detail how to use unbuffered CMOS inverters as rough linear amplifiers.
I have a hardcopy of the book. Unfortunately I will not be home for a while to take a picture of the relevant pages.

 

Here is one application note from National Semiconductor on 74C series gates.

http://www.bitsavers.org/components/national/_appNotes/AN-0088.pdf

 

Take the resistor out and see what happens. I think you will find a better signal at the output.

Did the previous circuit use the same logic family? Perhaps it was needed for reasons that no longer apply.

Yes, it used the same family. I'll do your suggestion tomorrow

Take the resistor out and see what happens. I think you will find a better signal at the output.

Did the previous circuit use the same logic family? Perhaps it was needed for reasons that no longer apply.

The output seems to be more or less the same.

 

RCA Semiconductor had an app note which described in wonderful detail how to use unbuffered CMOS inverters as rough linear amplifiers.
I have a hardcopy of the book. Unfortunately I will not be home for a while to take a picture of the relevant pages.

Sounds good. Could you post the name of the book?

 

Here is one application note from National Semiconductor on 74C series gates.

http://www.bitsavers.org/components/national/_appNotes/AN-0088.pdf

Interesting. Thanks!

 

Hello,

It is not a homework (I encontered this in an older design) but I asked to a senior electronics where I work and he couldn´t help me because he is more like an analog guy. It put the post in Homework because I think it is something "easy" and more fittable in here. Thanks to your comments give me a clue on how to calculate this gain but still a little bit lost about how to obtain the value of 47K resistor. I hope there are not silly questions to you or bother you in any way. I´m the kind of person that likes to know how to do stuff and how they really works before taking them from granted. I asked them in here after making a research myself before and not to be able to find an answer to this alone.

Sorry for the long response. And really thank you for your time.

Hello there,

Yes that inverter acts like an operation amplifier just that it has no non-inverting input, that's about it, and the linearity will not be as good as a real op amp. That section therefore is just like an OA inverting amplifier, which hints at what the 47k resistors does.

The 47k resistor works in conjunction with the 100 Ohm resistor just before it. This sets the (inverting) gain, and because it works like an OA the gain would be 47000/100=470, which is quite large. Because of that large gain, that inverter section may be being used to simply amplify the signal as well as clip it.
You would have to scope this out carefully.

For the first inverter section, that is biased with the 1M resistor in a similar way to the 47k in the second inverter section. The output may be low level hence the need for the amplifier that follows using the second inverter section.

As a side note, biasing gates into linear operation can be interesting because you can get a very high gain, although with high gain comes the problem of limited input range in order to maintain a linear, or should I say a pseudo linear, range.

The app note provides some interesting information.

 

But the real question is why linear operation is desired here. IMHO you want the opposite to clean up the square wave, not to amplify its flaws.

 

which of the two inverters are you refering to ?
both are being use din pseudo analog mode,
unbuffered CMOS devices, cna be thought of as very high gain amplifieres, when biased correctly, but are very noisy and none linear.
The inverter on the left, is being used to excite the crystal, and make a square ish wave form,
Thi scircuit is very high impedance and very critical of capacitance / inductance. Just applying a scope probe to any par tof the circuti on the left ha a high chance of affecting the oscilation, at best attenuating it , at worst, killing it totaly.
the onverter on the right , is being used as a pseudo buffer .
its high input impedance, along with the feedback circuit around it, convertes the roughly square ish wave of the crystal, to a true square wave.
Its output will chnage little if its probed with a scope on say 10:1 input range.
this might be of interest
https://www.ti.com/lit/pdf/szza043

 

But the real question is why linear operation is desired here. IMHO you want the opposite to clean up the square wave, not to amplify its flaws.

Hi,

It's actually simple.
The oscillator puts out an amplitude too small to drive a regular logic gate. By biasing the gate and providing a huge gain, the output should be fairly square anyway. That appears to be the intention here. So, in effect it should provide amplification as well as squaring.

 

Thank you everyone for your help! Thanks to all your comments I think I can understand how this circuits works and its intention.

 

Hi,

It's actually simple.
The oscillator puts out an amplitude too small to drive a regular logic gate. By biasing the gate and providing a huge gain, the output should be fairly square anyway. That appears to be the intention here. So, in effect it should provide amplification as well as squaring.

are the feedback resistors around the second inverter way to small in vlaue though, they are damping the oscilator

 

are the feedback resistors around the second inverter way to small in vlaue though, they are damping the oscilator

Hi,

I would think it's the other way around. The larger the resistors, the more damping would occur. That's because the resistors work in conjunction with the input capacitance to form a coincidental low pass filter. Some very high frequency amplifiers use very low value resistors like 50 Ohms. It's the RC low pass filter effect we end up seeing.

It is kind of strange they would use these components at 24MHz. Maybe you could check the normal switching speed on the data sheet see if that makes sense. I would think 10MHz would work but above 20MHz I'm not so sure. Some real world testing like he is doing would be good. If it looks like too much low pass filtering, then he'd have to find another way to do it. Using a 10x probe that is rated for at least 50MHz. He can also place a resistor in series with the tip to help isolate the probe from the circuit test point a little. The resistor cannot be too large though probably 1k max or it will distort the scope waveform too much.

Looking at the data sheet, it seems that 24MHz is pushing the envelope. The rise and fall times and the delay time make it look like it would barely work at that frequency.
He can also try placing another hex inverter stage on the very output and look at the output of that inverter with the scope instead.
What else he can do is try a lower frequency and compare that with what he sees now. He'll need a lower frequency crystal to do that though. See what happens around 10MHz or even lower.

 

Hi,

I would think it's the other way around. The larger the resistors, the more damping would occur. That's because the resistors work in conjunction with the input capacitance to form a coincidental low pass filter. Some very high frequency amplifiers use very low value resistors like 50 Ohms. It's the RC low pass filter effect we end up seeing.

It is kind of strange they would use these components at 24MHz. Maybe you could check the normal switching speed on the data sheet see if that makes sense. I would think 10MHz would work but above 20MHz I'm not so sure. Some real world testing like he is doing would be good. If it looks like too much low pass filtering, then he'd have to find another way to do it. Using a 10x probe that is rated for at least 50MHz. He can also place a resistor in series with the tip to help isolate the probe from the circuit test point a little. The resistor cannot be too large though probably 1k max or it will distort the scope waveform too much.

Looking at the data sheet, it seems that 24MHz is pushing the envelope. The rise and fall times and the delay time make it look like it would barely work at that frequency.
He can also try placing another hex inverter stage on the very output and look at the output of that inverter with the scope instead.
What else he can do is try a lower frequency and compare that with what he sees now. He'll need a lower frequency crystal to do that though. See what happens around 10MHz or even lower.

It's just the app notes I see using inverter logic, and the examples I have used tend to use Meg ohm value resistors

 

The question is why you would want to? CMOS gates should never be operated in between the off and on states. They basically look like a short circuit when the input is somewhere in the middle because both transistors are on.

I disagree. An old CD4xxx Cmos IC uses very low supply current when the output is at half the supply voltage and when the supply voltage is 10V or less. Then the output is far from being a short circuit, instead it is a fairly high impedance.
74HCxxx Cmos ICs draw a fairly high current when linear.