Hello. I am having a simple problem but couldn't help to solve it, I am doing a Asynchronous BCD with JK Flip flop, but I used to create an upward ones, and I don't know how to revert it or make it downward instead of upward. I also tried to use NOT gate, but didn't work. Below is the screenshot of my work. Hope you could help me with this. Thanks so much..

 

hi 15e,
Welcome to AAC.
What is the counting sequence of the circuit you have posted, using that display.?
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Welcome to AAC!

Hope you could help me with this.

Post your truth table and Kmaps.

Regarding your schematic style. You have the flip flops drawn sideways and ground always points down.

 

hi 15e,
Welcome to AAC.
What is the counting sequence of the circuit you have posted, using that display.?
E

Hello sir, its initial state is F (1-1-1-1), then first pulse is 0 (0-0-0-0) and so on...

 

Welcome to AAC!

Post your truth table and Kmaps.

Regarding your schematic style. You have the flip flops drawn sideways and ground always points down.

Hello sir, to be honest I don't know yet how to create the KMaps, and currently practicing in creating perfect truth table.

Regarding with the position of my JK flip flops, I am sorry for that cause it was a given instruction of my professor, not including the ground. Thank you so much sir.

 

I don't know yet how to create the KMaps, and currently practicing in creating perfect truth table

My fault. I thought you were designing a synchronous counter. You'll learn about synchronous counters when you learn about the limitations with asynchronous designs.

What do you think is required to have the counter go from 9 to 0 0 to 9?

EDIT: corrected count order

 

hi 15e,
You know what the Q outputs are doing during the count sequence, what do you think the NOT Q outputs are doing during the count sequence.??

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Update:
For your UP counter can you complete the missing 0s and 1s in this Count Table.?
I have done the first 5 states.
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Draw your flip-flop like this,

(except there ought to be a bubble on the /Q output, and bars over PRE and CLR)



Here is the corrected symbol:



Reference: http://hades.mech.northwestern.edu/index.php/Flip-Flops_and_Latches

 

A BCD down-counter means that the count will proceed from a count of nine down to zero. Should the count stop at zero or cycle back to nine? Look at a table of the individual bit states as the count goes from nine to zero. Note that the "A" bit changes its value for each clock pulse, i.e. alternating red and green transitions. Also note that a green transition always triggers a transition to the more significant bit on the left, but a red transition never does. (hint: that is a clue)

But the previous observation does not apply once the down counter reaches zero. So, have you determined what is supposed to happen once the down-counter reaches zero?

 

Good day sir(s)! First of all I just want to thank you all for giving me such tips and advises for me to solve my simple problem and to improve my work from self-learning, and I've got a solution already for the said problem, because of all your given tips and clues.



As it shows I have just inserted 'NOT gates' (Inverter) to all the 'Clock' for it the switch would turn into NGT.

So from its original counting: 0 (Zero) to F, it turns out now to F to 0 (Zero), and then resets back to F and so on...

I don't know if this is the right way or not, but I found this way solved my problem. Anyways, I'm doing the truth table for this and I don't have any idea on how to create the right one. Again, thank you so much sir(s) and madam(s) 'if any'.

 

As it shows I have just inserted 'NOT gates' (Inverter) to all the 'Clock' for it the switch would turn into NGT.

The inverters aren't needed because the flip flops have both polarity outputs. U9 isn't needed either.

Do you know the rule for connecting flip flops to get them to count up or down asynchronously?

Anyways, I'm doing the truth table for this and I don't have any idea on how to create the right one.

As far as I know, there's no (widely taught) formal design process for asynchronous counters. You just use the clock and output rules to get the counter to count in the right direction and decode counts to use for the preset/clear inputs.

EDIT: add (widely taught) qualification.

 

hi 15e,
Did you check as suggested how the /Q outputs where changing as the Q outputs counted Up.
Look at the sequence and let me know what you see.

BTW: it's not a BCD counter, it counts from 0 to 15, so it is Binary counter.
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