Asynchronous 4-Bit Counter

Thread Starter

Bob_Yang

Joined Nov 17, 2019
4
Hi, I'm a beginner for the digital circuit. Recently I encounter a problem when trying to implement a 4-bit counter by using Quartus. Following are my diagram and simulation outcome, the problem is why the simulation is not correct? I hope someone can help me, thanks!

Diagram
1573968834996.png

Simulation
1573968901554.png
 

SteveSh

Joined Nov 5, 2019
92
Quartus is a FPGA design tool from Intel.

Try asserting (taking it low) the reset early in the simulation sequence. The problem may be that the simulator assumes the flip flops come up in an unknown state. Once they're in an unknown state, even though they may be toggling, the simulator doesn't know what their state is.
 

Thread Starter

Bob_Yang

Joined Nov 17, 2019
4
Quartus is a FPGA design tool from Intel.

Try asserting (taking it low) the reset early in the simulation sequence. The problem may be that the simulator assumes the flip flops come up in an unknown state. Once they're in an unknown state, even though they may be toggling, the simulator doesn't know what their state is.
Yes, you're right. I just figured out what the problem is according to my professor's advice. thanks, anyway.
 

Thread Starter

Bob_Yang

Joined Nov 17, 2019
4
Hi, all, this problem is solved and I get the exact result I want now. thanks for your helpful advices.
So, I need to close this thread or mark it as solved?

Simulation
1574020915746.png
 

ci139

Joined Jul 11, 2016
778
besides the reset , another thing is which are the defaults and how the voltage and threshold levels are set for the gates . . .
 

ci139

Joined Jul 11, 2016
778
But glad found this site : learned ALOT from people here than that school : alot gained..Alot..wish can get degree from this site
You should study all things from all sources (directly) related to your (future) job ←
You can study everything else you're interested in but it's best to have a paper on ↑
 
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