AND gate with cmos transistor
we can create cmos AND gate with 3 nmos and 3 pmos transistor
Equation X=AB
AND gate cmos circuit= <-NAND--Inverter->
I want to size the transistor so that the output resistance is same as that of inverter with nmos W/L=3/2 and pmos W/L=6/2
inverter with nmos W/L=3/2 and pmos W/L=6/2
parallel pmos (L will double with same W)
pmos 1 W/L=6/4 and pmos 2 W/L = 6/4
nmos series ( W will double with same L)
nmos 1 W/L= 3/4 and nmos 2 W/L=3/4
transistor size for AND gate cmos
nmos 1 W/L=6/4
nmos 2 W/L=6/4
nmos 3 W/L=3/2
pmos 1 W/L=3/4
pmos 2 W/L=3/4
pmos 3 W/L=3/2
IS this correct sizing for AND gate
we can create cmos AND gate with 3 nmos and 3 pmos transistor
Equation X=AB
AND gate cmos circuit= <-NAND--Inverter->
I want to size the transistor so that the output resistance is same as that of inverter with nmos W/L=3/2 and pmos W/L=6/2
inverter with nmos W/L=3/2 and pmos W/L=6/2
parallel pmos (L will double with same W)
pmos 1 W/L=6/4 and pmos 2 W/L = 6/4
nmos series ( W will double with same L)
nmos 1 W/L= 3/4 and nmos 2 W/L=3/4
transistor size for AND gate cmos
nmos 1 W/L=6/4
nmos 2 W/L=6/4
nmos 3 W/L=3/2
pmos 1 W/L=3/4
pmos 2 W/L=3/4
pmos 3 W/L=3/2
IS this correct sizing for AND gate
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