Analog Design Questions

Thread Starter


Joined Jan 6, 2018

If our teacher gave us only the technology and input voltage = -x to x for designing a differential stage what equation can we extract from here?
The word technology refers to W or L of a transistor?
It seems tricky with the lack of details about it. Our job is to define the right W/L .
Is this design ok?



Joined Oct 21, 2014
Yes, the technology defines minimum channel length that is possible to be manufactured using this process. In your case there are transistors with L=0.35 so I assume that the teacher defined technology as CMOS 0.35um what confirms also the .lib declaration ("_035" part).

Some remarks on your design:
1. M5 should be in the diode connection. M5 and M6 are the current mirror.
2. Body of M1 and M2 may be connected to ground. Usually dual well process is not used as it's more expensive.
3. R1 = 10k is a bit low resistance. Usually CMOS designs works with big load resistances, that are mega Ohms, e.g. gate of MOS transistors. In your design the bias current is equal to 100 uA. Hence, your output will be from -1V to 1 V.

Have you tried to run the simulation?

I think that the design task is correct. I think the aim is to make your class familiar with basic opamp structure. You'll find a lot of help in analog CMOS books e.g. Razavi or Baker. For online help, you may also look here page 50 (ch. 3.1.1).