Hello everyone,

Can someone help me figure out what I'm doing wrong? I can't seem to fix this error. I'm new to allegro and one footprint away from finishing my board.

 

I don't use Allegro and, of course, cannot open the attachments.

I suspect there are similarities to EAGLE, which I use. A pad is made of several layers, including a signal layer. If various clearances violate DRC (design rules), you will get an error. Eagle will show where those violations are in DRC. Have you checked those clearances?

Here is an example from Eagle:


Things to try:
1) Try a known "good" pad and see what happens. Compare its design with your failed design.
2) Go to your design rules and "ignore" pads.
3) Adjust clearances and such for your pads.

Edit: Another possibility (unlikely) is that you have a via on a pad. That used to give an error at Oshpark, but not with my program per se.