how can i use 24 bit adder with enable pin in ise 12.1?​

 

Lots of ways. Draw one in the schematic. Roll your own using HDL. Probably the easiest thing to do will be to use CoreGen to do all the work for you. Then you just instantiate it (using the .veo or .vho file) in your code. I'm sure there's a way to instantiate it into a schematic too.

You need to give us a MUCH better description and possibly code/schematics before we can really help you beyond that.

 

This is actually quite simple. In VHDL you can say:

---------------------------------------------------------
signal inputA, inputB, sum : std_logic_vector(23 downto 0);
signal enable : std_logic;
---------------------------------------------------------
process(enable,inputA,inputB)
    if(enable='1')then
        sum <= inputA + inputB;
    end if;
end process;
---------------------------------------------------------

ISE should know exactly what to do with this to get you your desired result.