I was trying to configure the ADC for sample time and convert time and gone through the below video
STM32 ADC Conversion Time: Formula, Calculation & Verification
I am really surprised with the below
Sampling time is 239.5 ADC cycles
Why would i require 239.5 ADC cycles to sample, I am assuming that the 239.5 ADC cycles is the sample and hold circuit.


From the above i can understand that if i provide minimum sample time that is enough, why should i give more time than required?
STM32 ADC Conversion Time: Formula, Calculation & Verification
I am really surprised with the below

Sampling time is 239.5 ADC cycles

Why would i require 239.5 ADC cycles to sample, I am assuming that the 239.5 ADC cycles is the sample and hold circuit.


From the above i can understand that if i provide minimum sample time that is enough, why should i give more time than required?
