ADC S&H circuit

Thread Starter

Vihaan@123

Joined Oct 7, 2025
247
I was trying to configure the ADC for sample time and convert time and gone through the below video
STM32 ADC Conversion Time: Formula, Calculation & Verification
I am really surprised with the below 1780916725950.png

Sampling time is 239.5 ADC cycles 1780916766888.png

Why would i require 239.5 ADC cycles to sample, I am assuming that the 239.5 ADC cycles is the sample and hold circuit.
1780917113984.png

1780917146112.png

From the above i can understand that if i provide minimum sample time that is enough, why should i give more time than required?
 

WBahn

Joined Mar 31, 2012
32,852
Did you not see that that was an EXAMPLE and that it was used to point out "This example clearly shows how increasing the sampling time significantly affects the total conversion time, even though the conversion cycles remain fixed."?

Instead of going to some website, which may or may not have good information, you might try actually looking at the official STM32 documentation.
 

Thread Starter

Vihaan@123

Joined Oct 7, 2025
247
I was only curious to know if anyone uses such sampling even in cubemx for stm32 code generation software
1780918375886.png
I see him providing option for high sampling time.
 

Rf300

Joined Apr 18, 2025
90
First of all you have to read carefully and understand(!) the chapters about the ADC in the data sheet AND in the user manual. This is hard work, since the ADC's (and most of the other peripherals of STM32) are quite complex. After that you can try to configure the device in CubeMX. The corrrect selection of the sampling time is crucial for the correctness of your ADC results. It depends on things like ADC clock, output impedance of your analog signal and so on.
 

Futurist

Joined Apr 8, 2025
759
I was trying to configure the ADC for sample time and convert time and gone through the below video
STM32 ADC Conversion Time: Formula, Calculation & Verification
I am really surprised with the below View attachment 368134

Sampling time is 239.5 ADC cycles View attachment 368135

Why would i require 239.5 ADC cycles to sample, I am assuming that the 239.5 ADC cycles is the sample and hold circuit.
View attachment 368137

View attachment 368138

From the above i can understand that if i provide minimum sample time that is enough, why should i give more time than required?
I've found AI to be helpful with such questions. If you ask your question (very clearly, not too informal) of say Copilot, you'll probably get some clarity. Begin with background info like "I have a question on STM32 ADC peripheral" then ask your question, you should quote (copy/paste) from the datasheet too.

Also give AI the datasheet URL, tell it the specific MCU model number etc. I've found that the more formal the problem domain is, and the more clearly one writes, has a huge effect on the quality of its response.
 

Irving

Joined Jan 30, 2016
5,128
Also read ST's application note on oversampling AN5537 (attached)

You only need multiple samples to improve resolution and combat noise. You'll only know whether that's necessary once you have the hardware up and running and can run some exploratory software to measure the quality of the conversions in the live environment.
 

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