Hello all!
I was reading that Karnaugh maps reduce larger logic designs. It seems that when using the Karnaugh map with a paper and pencil , we can work with at most 8 inputs. What do people do when there are 300 inputs? What solutions do people use for large number of inputs? Ty for all the replies!!

 

Karnaugh maps are only really any use up to 4 inputs, as a human exercise,
above that , computer algorithms are the rule, don't do it by hand.

as to the algorithum,
many many around, most proprietary to the tool manufacturers, and built into tools liek ASIC / FPGA developers

 

Karnaugh maps are only really any use up to 4 inputs, as a human exercise,
above that , computer algorithms are the rule, don't do it by hand.

as to the algorithum,
many many around, most proprietary to the tool manufacturers, and built into tools liek ASIC / FPGA developers

Ty, so is it ok to assume that if I were to use a FPGA to build a traffic light system with 50 inputs, the FPGA software that I use would automatically take care of the "Karnaugh Map" crunching?

 

Oh yes, big style,

I assume your coding in an RTL,
using a state machine ?

your not codding by "equations" are you..

 

Hello all!
I was reading that Karnaugh maps reduce larger logic designs. It seems that when using the Karnaugh map with a paper and pencil , we can work with at most 8 inputs. What do people do when there are 300 inputs? What solutions do people use for large number of inputs? Ty for all the replies!!

It ceased to be a problem some decades ago with the advent of Hardware Design and Synthesis languages like Verilog and VHDL. The implementation boils down to a single FPGA chip for quite complex designs.