I am trying to create an adjustable low pass filter for a direct digital synthesis system. The output of the DDS will vary from 1 MHz to 12 MHz in intervals of 1 MHz (1M, 2M, ...,11M, 12M). I am trying to keep the spurs and harmonics down to -50 dBc. Currently, my plan to achieve this is to have a nmos controlled capacitor bank, but the input and output capacitances of the FETs are affecting my cutoff frequencies. Is there a way around this? I have also looked into using varactors, but they require a variable voltage source, and I am trying to keep the design as simple and efficient as possible. Attached is my spice schematic and simulation for one of the cases.

 

If there was a cheap way of using dds output the big three radio manufacturers would have tried it. they all use a combo of pll, mixers and dds to reduce phase noise.

 

Something like this -

http://www.arrl.org/files/file/QEX_Next_Issue/July-August2017/Gionetti.pdf


Regards, Dana.