555 Timer for Latch-up Protection

Discussion in 'Embedded Systems and Microcontrollers' started by Defuzzification, Nov 6, 2014.

  1. Defuzzification

    Thread Starter New Member

    Nov 6, 2014
    My project is an ARM board to be used on a cube satellite. Due to high radiation levels, we require a reliable way to detect and correct latch-up errors in memory. This is easily done with a current sensor as most manufacturers specify the latch-up current for memory chips. We have selected current sensors (INA226AIDGST) that have a software-configurable current threshold. If a high current is detected, an open drain interrupt pin will give a low signal. This interrupt should cause a high side PMOS to be switched off as fast as possible (5 usec would be competitive). This PMOS should remain off for a minimum amount of time (50 to 200 msec). We are considering using a bipolar 555 timer which should be reasonably radiation tolerant. The problem is, my group has limited experience with 555 timers. If someone has some idea of how to achieve what I have described, please share it. Thanks in advance.
  2. Alec_t

    AAC Fanatic!

    Sep 17, 2013
    The low signal on the interrupt pin could easily be used to start a 555-based 200mS timer whose high output would (with a bit of help) turn off the PFET. I have no idea how reliable a 555 would be under intense radiation though.

    I'm curious as to why you choose a bipolar 555 rather than a CMOS one, considering that the current sensor contains MOS devices?
    Last edited: Nov 6, 2014
  3. ErnieM

    AAC Fanatic!

    Apr 24, 2011
    One thing I thought of out driving this morning was simply removing the power from the memory chip may not reset from the latch-up. This is due to built-in diodes on many pins to protect from ESD hits on the lines themselves. It is entirely possible to power on a chip (especially CMOS) thru an input set to high while no Vdd is connected.

    Aside: I'm not convinced you actually need the 555 chip: The INA226AIDGST may be able to drive the MOS pass element itself, and provide a delay by a simple RC network. However, my muse is silent as to the practicable parts such as where that RC is actually connected.