Hello All,

I'm wondering if someone could help me understand what the attached circuit is trying to accomplish. I'm particularly looking to figure out what the diode is used for.
A point that might be of relevance: I believe the TR+ input of the CD4098 would tolerate 4V and needs 11V before it triggers.

 

The diode stops the Q output of the 4027 from interfering with the timing of the 555 chip.

As for what it is all trying to do...I don't know.

 

Thanks for the response, #12.
In that case, I wonder why have any connection between Q and the timer? The timer output feeds a clock and nothing else so why not just leave it running?

 

If the Q output of the 4027 is low, and can sink current, it will completely stop the trigger signal from getting to the 4098 chip. Adjusting R105 can allow the 4027 Q output to slow down the 555 chip.

I still don't know what the overall goal is. I'm just pointing out how these things are interacting. Apologies for that.

 

No apologies necessary. I absolutely appreciate all input.

So you think the CD4098 is getting triggered by the 555? I hadn't considered that. I assumed the CD4098 was triggering off the Q output of the flip-flop. I will consider your point now.

 

U6B (the 4027) has it's power pins to +15v and GND, and the Q output is connected directly to U4A's TR+ input. The 555 will have only minimal effect on U4A/U6B, as the impedance of the U6B's Q output will be low relative to R104 & R105.

However, if U6B's Q output is low, depending on R105's setting, it could prevent the 555 timer from reaching the threshold value, thus keeping the OUT of the 555 high.

[eta]
I confirmed the assertion of the effect on the 555 via a simplified simulation. It's a way of not only disabling the 555, but also establishing the charge voltage on the timing cap for when the 555 is allowed to resume; thus changing the delay from when Q returns high to when the 555 output goes low.

Since R1+R2=44k, and the maximum value of R104+R105 can be is 50.47k Ohms, the default threshold level is 2/3 Vcc,
and the voltage drop across the diode will be around 0.5v at such low current (<200uA), the threshold voltage can't be reached and the 555 output will be "stuck" high until U6Bs' Q output goes high.
See the attached. In the simulation, I replaced the 4027 output Q with a simple voltage source that outputs a square wave, and R104/R105 with a single fixed 40k resistor. Sine the 4098 was not relevant (TR+ being a high-impedance input), it was omitted.

 

Thanks for another input. That makes a lot of sense and is very helpful. I had concentrated a lot on the assumption that Q of U6B was used to trigger TR+. So if that point is fixed at a certain voltage even when Q was low, I thought how could U4A ever trigger since the point was never allowed to go lower than what was required for triggering on TR+. But now I think the only time TR+ actually triggers is at power up when that point transitions from 0 to 15V, before settling on its fixed point. Does that sound reasonable?

In that case, my next question is what happens around the 555 at power-up while Q is still low? So first there is a direct path between the 15V of the 555 and TR+? The capacitor starts to charge up until a certain point? (What determines the initial charge on the capacitor?) Most importantly how is [size of] the charge voltage on the cap established and kept fixed until Q goes high?

 

I had overlooked your calculation explanation when I responded. I will look at them now. Thanks again.

 

I had concentrated a lot on the assumption that Q of U6B was used to trigger TR+.

It is.

So if that point is fixed at a certain voltage even when Q was low, I thought how could U4A ever trigger since the point was never allowed to go lower than what was required for triggering on TR+.

U6B Q should swing from nearly 0v to nearly 15v. TR+ is a relatively high-impedance input.

But now I think the only time TR+ actually triggers is at power up when that point transitions from 0 to 15V, before settling on its fixed point. Does that sound reasonable?

It's impossible to tell from this schematic what sets or resets Q6B, as those inputs aren't shown connected to anything. If actual CMOS inputs were left floating like that, Q6B's outputs would toggle/oscillate unpredictably.

U4A's RESET input has a 0.1uF cap on it; but no pull-up resistor - so that cap won't have any effect on the RESET input. Since U4A's state depends upon U6B's state, and U6B's state cannot be determined because it's control inputs are not shown, the whole circuit is up in the air. If there is more to the circuit than what is shown, you should include that information.

In that case, my next question is what happens around the 555 at power-up while Q is still low?

If U6B's Q is low, everything above R104 connected to Q will be low.

So first there is a direct path between the 15V of the 555 and TR+?

No, there is not.
R104, R105, D103, R29 and R30 are all in series, and all between +15v and the TR+ input.

The capacitor starts to charge up until a certain point? (What determines the initial charge on the capacitor?) Most importantly how is [size of] the charge voltage on the cap established and kept fixed until Q goes high?

On initial power-up, there is no voltage across C9 (C1 in my simulation; but I didn't show initial power-up state in the simulation).
If the Q output of U6B is low, then the voltage on C9 will be about:
( (15V-V(D103)) / (R104+R105+R29+R30) ) *( R104+R105+V(D103))
after a sufficient amount of time passes. The voltage across D103 will be about 0.4v to 0.5v due to the low current through it and the resistors.
15-v(D103)/(22k+22k+50k+470) ~= 14.6/94.47k ~=154.5uA
154.5uA * (50k+470) ~= 7.79v.
The threshold value will be 2/3 of Vcc, so 15v*2/3=10v. The output of the 555 will stay high until the charge on C9 reaches the threshold.

As I've already suggested, R105 provides the means to adjust the range of C9's voltage from nearly the threshold down to nearly 0v.,

 

Hello again and thanks again.

That's another helpful point about floating inputs. The Set input is driven by a pulse that switches on and off and the reset is driven by the output of an AND gate.
I did the simulation and saw what you pointed out about Q switching from 0V to 15V. Yes, I also see the variable resistor (represented by R3, R4) causes the voltage on the capacitor to vary from very low to [around >8V?] near threshold. The first two diagrams below are of those simulations.
When the circuit is simulated as it is in PSpice, I see something slightly/very different, the Q doesn't switch all the way to 0V (third diagram). What could be a reason for that? Is that simply a result of the behavior of floating inputs or is there something else? (the simulation is done with a pulse input to SET but floating RESET).
Also, What is the advantage of having an option of at what value to set the initial voltage on the capacitor? Is it to speed up its initial charge up/discharge time once the output is activated? That didn't seem like such a big advantage since it only affects the first cycle of the output. Or is that a good enough reason?

 

The Set input is driven by a pulse that switches on and off and the reset is driven by the output of an AND gate.

As far as the impulse on SET; if it is a switch that is open in one position, there needs to be a pull-up or pull-down resistor so that the input is never left floating.

I did the simulation and saw what you pointed out about Q switching from 0V to 15V. Yes, I also see the variable resistor (represented by R3, R4) causes the voltage on the capacitor to vary from very low to [around >8V?] near threshold. The first two diagrams below are of those simulations.

OK, good.

When the circuit is simulated as it is in PSpice, I see something slightly/very different, the Q doesn't switch all the way to 0V (third diagram). What could be a reason for that? Is that simply a result of the behavior of floating inputs or is there something else? (the simulation is done with a pulse input to SET but floating RESET).

Don't leave inputs floating, even in simulations. Simulations are only approximations of real-world components, and a considerable number of "shortcuts" are frequently taken in the models. If every possible subtle nuance were modeled, your simulations would take a very, very long time to run, and would generate vast amounts of data.

The LTSpice models for the 4000 series are macromodels rather than discrete component models. They're actually more robust than a real-world 4000 series CMOS IC is. The LTSpice supplied NE555 is also a "shortcut" macro; the output voltage swing is that of a CMOS 555, but can source/sink far more current than a real-world CMOS 555 could.

Even slight loading will impact the maximum/minimum voltages that a real 4000 series IC will output. You will see that if you look in a datasheet.

Also, What is the advantage of having an option of at what value to set the initial voltage on the capacitor? Is it to speed up its initial charge up/discharge time once the output is activated? That didn't seem like such a big advantage since it only affects the first cycle of the output. Or is that a good enough reason?

It gives the simulation a starting point. Since the 555 is an astable multivibrator, it can take a considerable amount of time for a SPICE simulation engine to determine what the initial operating point will be; and it may not be able to calculate it due to convergence problems. Using .ic's gives it known value(s), so that it can calculate the other parameters rapidly. Another way to do it is to use the startup function on the .tran statement; that forces all voltages to 0v during the startup. The uic option tells it to skip figuring out what the initial operating point will be, but you can wind up with huge spikes in the simulation for the first few moments in time. If you decide to use uic, you'll probably want to start saving data AFTER the first millisecond or so.

 

Okay, got it about the simulation differences. Thank you.
The impulse for SET comes through an optocoupler. It has a pull-down resistor at the emitter of the optocoupler transistor for when the transistor is turned off.

Finally, I meant to ask about the real world implications of varying the initial voltage on the cap using the pot. What do we get by being able to set the voltage on the cap from near 0 to near threshold? Why not just leave it with a fixed resistor that sets a constant known value for the capacitor when the timer output is high?

 

I mentioned that in my first reply to this thread, where I said:

...changing the delay from when Q returns high to when the 555 output goes low.

What does the larger circuit do? I mean, what is this small section of circuitry a part of? Without knowing that, it's hard to guess why someone would want to be able to vary the delay from when the Q output goes back to 15v and the output of the 555 falling.

 

Yes, you did. That explains it. I have broken up a larger circuit and I'm working through the rest. This had me baffled. Thanks lots, have a great day.