The standard operation of the 4017 is to tie the "clock inhibit" line (pin 13) low and set reset (pin 15) low and then pulse clock (pin 14) to have the outputs change.
To make my pcb design much easier, I was thinking of tying the clock line to high then pulse the "clock inhibit" line since according to a datasheet both of those lines are tied to the same nor gate but one line is through an inverter to the gate.
Is there any disadvantages of functional concerns I should be aware of if I used the "clock inhibit" line as the actual clock instead of the clock line?
I'll be tying the reset and clock line to individual outputs of a D latch
To make my pcb design much easier, I was thinking of tying the clock line to high then pulse the "clock inhibit" line since according to a datasheet both of those lines are tied to the same nor gate but one line is through an inverter to the gate.
Is there any disadvantages of functional concerns I should be aware of if I used the "clock inhibit" line as the actual clock instead of the clock line?
I'll be tying the reset and clock line to individual outputs of a D latch