4017 Decade counter modifying clock

Thread Starter

mike_canada

Joined Feb 21, 2020
31
The standard operation of the 4017 is to tie the "clock inhibit" line (pin 13) low and set reset (pin 15) low and then pulse clock (pin 14) to have the outputs change.

To make my pcb design much easier, I was thinking of tying the clock line to high then pulse the "clock inhibit" line since according to a datasheet both of those lines are tied to the same nor gate but one line is through an inverter to the gate.

Is there any disadvantages of functional concerns I should be aware of if I used the "clock inhibit" line as the actual clock instead of the clock line?

I'll be tying the reset and clock line to individual outputs of a D latch
 

AnalogKid

Joined Aug 1, 2013
8,468
The only possible issue is that the clock input has hysteresis and the inhibit input does not. If your incoming clock signal has clean, fast rise and fall times, no problem.

ak
 

Analog Ground

Joined Apr 24, 2019
397
The standard operation of the 4017 is to tie the "clock inhibit" line (pin 13) low and set reset (pin 15) low and then pulse clock (pin 14) to have the outputs change.

To make my pcb design much easier, I was thinking of tying the clock line to high then pulse the "clock inhibit" line since according to a datasheet both of those lines are tied to the same nor gate but one line is through an inverter to the gate.

Is there any disadvantages of functional concerns I should be aware of if I used the "clock inhibit" line as the actual clock instead of the clock line?

I'll be tying the reset and clock line to individual outputs of a D latch
One caution. All the timing specifications associated with the clock and clock inhibit go out the window. The timing specifications are not meant to apply to these inputs when used in the way you propose.
 

dl324

Joined Mar 30, 2015
10,761
Is there any disadvantages of functional concerns I should be aware of if I used the "clock inhibit" line as the actual clock instead of the clock line?
What is the nature of the clock? Will it be noisy or have a long fall time? Which 4017 variant will you be using?

AFAIK, Nexperia HEF4017 is the only manufacturer that claims to have Schmitt triggers on both clock inputs (though they don't show any on the logic diagram or specify longer allowable rise/fall times on the clock signals.

Other manufacturers that I've checked show a Schmitt trigger only on the clock input and say rise time can be 20us (or unlimited for RCA and TI). TI's NSC datasheet shows 20us.
 

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Thread Starter

mike_canada

Joined Feb 21, 2020
31
I don't want to only use one certain manufacturer to get results. The input to the clock is something I can control in terms of speed, and I think the signal will be clean since the signal comes from 74HC573 D latch and the input of the 4017 clock is connected very close to it (chips are < 2cm away from each other). But if I were to work this my way, what should I use as a worst-case scenario for timing? and lets assume the chip (4017) has the worst logic IC's built into it.
 

dl324

Joined Mar 30, 2015
10,761
But if I were to work this my way, what should I use as a worst-case scenario for timing?
If you use questionable design techniques, you could find that your circuit won't work if you have to replace a marginal device.

People with formal training will use conservative design practices if they care about their reputation.
 

Analog Ground

Joined Apr 24, 2019
397
To make my pcb design much easier,...
Making a design decision of this magnitude to accommodate a PCB layout challenge is a bit of "the tail wagging the dog". Normally, circuit changes are limited to gate or pin swapping. Perhaps you could post your PCB layout and let us suggest a way around your issue?
 

ElectricSpidey

Joined Dec 2, 2017
1,160
As long as you understand the counter will advance on the negative edge and not on the positive edge, and have a good clean signal, everything will be fine.

I have been clocking 4017s using the inhibit pin instead of using an inverter since...forever.
 

Thread Starter

mike_canada

Joined Feb 21, 2020
31
Ok, I didn't think I had to, but I decided to experiment with a simple 4017 circuit hooked to a 555 timer with timer output driving a clock inhibit pin with a 330 ohm resistor and everything worked as expected. I looked at the 4017 chip itself and it seems to have the old texas instruments logo on it, but I bought it from a shop in thailand. Nevertheless, the part still works.
 

dl324

Joined Mar 30, 2015
10,761
I decided to experiment with a simple 4017 circuit hooked to a 555 timer with timer output driving a clock inhibit pin with a 330 ohm resistor and everything worked as expected.
There you go again with your marginal designs.

NE555 and the like are not guaranteed to drive CMOS inputs.

The guaranteed HIGH output voltage at VCC=5V is 2.75V, with 3.3V typical. CD4017 operating at 5V require 3.5V for a HIGH input.
clipimage.jpg

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ElectricSpidey

Joined Dec 2, 2017
1,160
That data sheet clip does not give a source current for the Vcc = 5V rating, my guess would be closer to 4.1 or so into a high impedance load.

Those ratings look like the ones I have seen for 100mA @ Vcc = 5V.

NE555.JPG
 
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