4017 decade Counter modification

Discussion in 'Digital Circuit Design' started by haythamhakla, Apr 10, 2017.

  1. haythamhakla

    Thread Starter New Member

    Apr 10, 2017
    7
    0
    The way the 4017 counter works is that it turns the next output on for each clock cycle. For example, if output 0 is on, on the next clock cycle, output 0 will be off and output 1 will be on instead.
    My question is : is there another IC that does the same thing, but keeps the previous outputs on. For example, on the first clock cycle, output 0 is on; on the next clock cycle, output 1 in on and output 0 is still on...etc... on the last clock cycle, output 9 is on along with all the other outputs. On the next clock cycle, the counter is reset and output 0 is on and all the other outputs are off.
    If no such IC exists, is there a way to implement this desired logic with the 4017 or any other ICs? ( adding latches to the outputs etc...)
    Thanks for your feedback.
     
  2. ericgibbs

    Moderator

    Jan 29, 2010
    5,446
    1,020
    hi Hay,
    Look up Shift Registers, Serial to Parallel.
    E
     
  3. crutschow

    Expert

    Mar 14, 2008
    19,523
    5,444
    Basically to use the 74HC595 shift-register that Eric posted, you tie the "A" input to a logic one and provide pulses to the clock input.
    This will sequentially transfer a logic 1 through the shift-register for each clock pulse, leaving all the previous outputs high.
    When the last output reaches a logic 1 you use that signal to reset the shift-register.
    If you want the last output to stay high for a complete clock pulse, then you will need to add a flip-flop to control the reset, since the reset input is asynchronous (clears the shift-register immediately).
     
    Last edited: Apr 10, 2017
  4. AnalogKid

    AAC Fanatic!

    Aug 1, 2013
    7,006
    1,985
    Internally, a 4017 is a shift register and decoding gates, not a true counter. What you are describing as an alternate type of counter is actually a shift register.

    ak
     
  5. crutschow

    Expert

    Mar 14, 2008
    19,523
    5,444
    Here's an LTspice simulation using an 74HC164 shift-register that does your stated sequence, advancing one output on each clock rising edge.
    The 74HC74 flip-flop clears the SR for one clock-pulse after output Q7 goes high.

    R1C1 generate a short pulse for the reset.
    All outputs then stay low for one clock-pulse before the sequence again starts.
    (If the FF /Q output were connected directly to the MR input then all outputs would stay low for two clock pulses instead of just one.)

    More than one SR can be daisy chained if you want more than 8-bits output, with the FF reset circuit connected to the last SR in the chain.

    Make sure you connect all unused FF input high.

    upload_2017-4-10_14-50-45.png
     
    Last edited: Apr 10, 2017
    ericgibbs likes this.
  6. haythamhakla

    Thread Starter New Member

    Apr 10, 2017
    7
    0
    Thank you @crutschow and @ericgibbs for your feedback. I think I got your point. A shift register should do the job in my case.
    Thanks a lot your effort and the cool simulation!
     
Loading...