4 bit JK register - Xilinx [Schema+VHDL]

Create a structural scheme of modulo 16 register with JK flip flops in which the value of 0 is active input signal with a parallel read and write, where writing is managed independently of the clock signal.
To be exact, I have 4 inputs I0, I1, I2, I3 - each into separate JK ff - and LD (LOAD signal). [Easier to gasp with pictures in attachment]
I have 4 outputs Q0, Q1, Q2, Q3.

First I had to analytically solve this using NAND logical circuits and an extra RD signal (truth tables etc. and ):
Sorry that language on the picture isn't English.

Secondly, I had to create similar schema in Xilinx:

I could only show half of the schema so it could be understandable, but other half is exactly the same. And it is correct, I've run the following simulation on it:


Thirdly, I had to write VHDL code, based upon later I would make VHDLTestBranch. And after that I would have to create *.bit file for programming of FPGA board.

Might also note that we are using FPGA:
Input signals should be at this values, when I want to simulate it: I0=1, I1=1, I2=0, I3=0, LD=1.

I found how VHDL code looks for one JKFF.
And this is complete project (mediafire link). - that I did so far...

So, my question is, can anyone help me understand how to manually write VHDL for 4JK ff. given statements that I made above?