Hi. I'm designing an 8-bit computer using 74HC series logic, and rather than outputting a single number to a 7-segment display I want to output to a monitor. I'd like the resolution to be 320x200, like the C64, having a 40x25 character array (1,000 bytes in RAM) that my display circuit can read and output to the monitor.
Taking a good deal of inspiration from the Masochist's Video Card, the logic circuitry for generating the sync pulses seems pretty straightforward, as long as you have the correct timings. Their example uses the 800x600 60Hz standard, but divides the horizontal timings by 4, leaving the vertical as is, therefore reducing the clock speed required from 40MHz to 10MHz - a restriction based on the speed of their 74LS series chips.
Is it possible to divide BOTH the horizontal and vertical timings?
Using the 640x480 timings, I can halve both to 320x240, which would (in theory as far as I can figure out) quarter the required clock speed. Problem is that the vertical timings aren't divisible by two:
480 Lines / 2 = 240 - OK
11 Front Porch / 2 = 5.5 - Round up or down?
2 Sync Pulse / 2 = 1 - OK
31 Back Porch / 2 = 15.5 - Round up or down?
So the logical thing to do would be to run 320x480 at 12.585MHz (25.17MHz / 2), and just double up pixel data every two lines, with black areas for the extra 80 pixels, giving an effective 320x200 pixels.
Next problem is that I can't seem to source a 25.17MHz crystal or oscillator. I've got a 25MHz crystal, so can divide by two to make a 12.5MHz pixel clock, or by four to make a 6.25MHz pixel clock. (The reason I mention that last value is the Gigatron computer uses a 6.25MHz clock, which also drives the VGA output).
How does the deficit 0.085MHz affect the timings (12.585 - 12.5)? Or will modern LCD monitors (which I'll be using) cope with the discrepancy and lock onto the signal regardless?
Thanks in advance!
Taking a good deal of inspiration from the Masochist's Video Card, the logic circuitry for generating the sync pulses seems pretty straightforward, as long as you have the correct timings. Their example uses the 800x600 60Hz standard, but divides the horizontal timings by 4, leaving the vertical as is, therefore reducing the clock speed required from 40MHz to 10MHz - a restriction based on the speed of their 74LS series chips.
Is it possible to divide BOTH the horizontal and vertical timings?
Using the 640x480 timings, I can halve both to 320x240, which would (in theory as far as I can figure out) quarter the required clock speed. Problem is that the vertical timings aren't divisible by two:
480 Lines / 2 = 240 - OK
11 Front Porch / 2 = 5.5 - Round up or down?
2 Sync Pulse / 2 = 1 - OK
31 Back Porch / 2 = 15.5 - Round up or down?
So the logical thing to do would be to run 320x480 at 12.585MHz (25.17MHz / 2), and just double up pixel data every two lines, with black areas for the extra 80 pixels, giving an effective 320x200 pixels.
Next problem is that I can't seem to source a 25.17MHz crystal or oscillator. I've got a 25MHz crystal, so can divide by two to make a 12.5MHz pixel clock, or by four to make a 6.25MHz pixel clock. (The reason I mention that last value is the Gigatron computer uses a 6.25MHz clock, which also drives the VGA output).
How does the deficit 0.085MHz affect the timings (12.585 - 12.5)? Or will modern LCD monitors (which I'll be using) cope with the discrepancy and lock onto the signal regardless?
Thanks in advance!