Hey all, the first image attached is a half-adder circuit with the simulation and timings, are the sum & carry delay timings right? If not how do I calculate them correctly? The simulation shows the start and end point (blue and yellow vertical lines) and the T1-T2 is how I calculated it at first.

The second image attached is a 3-bit synchronous binary counter with timings in (ns), again I don't think that the timings are right, how would I set up the T1 and T2 lines to find out the period of most significant bit and the clock transition to output delay?

 

Hi,

In general you have to follow the signal through sequentially and consider all possible states because you might have different delays based on state. You also have to consider if there is a difference for low to high transitions and high to low transitions. This is just a general guideline.

 

Your first set up seems completely wrong to me if you are trying to calculate the delay through a combinatorial circuit such as a half adder. The delay you are looking for is the amount of time it takes between an input changes and when any resulting changes in the output occur. The overall delay is the worst case delay for any of the inputs to any of the outputs under and possible conditions.

 

Your first set up seems completely wrong to me if you are trying to calculate the delay through a combinatorial circuit such as a half adder. The delay you are looking for is the amount of time it takes between an input changes and when any resulting changes in the output occur. The overall delay is the worst case delay for any of the inputs to any of the outputs under and possible conditions.

I think I'm getting it, now trying to find the gate delay by using truth tables. Here are truth tables for half-adder and full-adder. So to find the sum and carry delays do I just need to follow the gates to 'sum' and 'carry' respectively and calculate the delays that way? So would a 'Not' gate be a 0 for the 'Sum' line in the half-adder circuit for example?

 

A "delay" is a concept involving time.

A truth table has absolutely no information about time.

The delay of a circuit is very dependent on the exact implementation of the circuit. A classic example is an XOR gate. There are several different common implementations and they have significantly different delays even using the same technology (such as minimum-gate transistors in a particular CMOS process).

But, if I'm understanding you correctly, when you say, "follow the gates" you are on the right path (no pun intended).

But then you lose me when you try to give your example.

You need the logic schematic for the implementation of your circuit.

Or you need to do the appropriate simulation (or make the appropriate measurement in the lab).