... and you have no freaking idea what the giants, whose shoulders we stood on, accomplished.....

Historically, there has always been the tendency of judging the past using modern standards... that's a common mistake. Think of how unfair it would be if we were to criticize Edison for not having thought of the LED instead of his primitive, fragile, bulky, short-lived, heat-producing, energy-wasting light bulb.

EDIT: I forgot to add the word dangerous to that list.

 

I had no idea they went back to NMOS and PMOS devices

Techs had told me for years never to use NMOS or PMOS EEPROM chips because of latching problems

They used NMOS and PMOS back in the 80's. They made us change all the NMOS and PMOS EEPROM chips to CMOS EEPROM chips because of latching problems and power was less using CMOS EEPROM chips.

The first Z80 was NMOS and it caused errors of latching problems and would draw to much current.

 

That's an excellent point. I see no reason why there can't be multiple experimental pathways, with only a couple of winners. Nobody ever said you had to get it right the first time. Microsoft and Intel won for reasons nobody could anticipate in 1968 or 1975.

 

I disagree. We always knew that CMOS would eventually win because because the power dissipation problems limited every other technological competitor. Reducing the feature size while increasing the wafersize was evident by the early 1980's. We also knew there was a successor to visible light lithography.

No one was thinking that CMOS would be running at 5GHz and feature sizes would be in the 10nm range. Even people in the industry were saying they were headed towards a cliff. Luckily scientists and engineers keep finding a way to extend Moore's Law. But I remember talking to a process engineer in the mid-90's and he was predicting the end a few generations after 250nm. Well they're still finding ways, albeit painful because EUV lithography is late, to do it and state of the art is around 10nm.

 

So all SMT/SMD IC chips and circuit boards that are powered by 3.3volts are Nmos and Pmos not cmos?

 

Techs had told me for years never to use NMOS or PMOS EEPROM chips because of latching problems

They don't know what they're talking about. You need a 4 layer diode to latch up. You don't get that until you have NMOS and CMOS on the same die. The problem with NMOS and PMOS only designs is that they had resistors that increased power dissipation. With CMOS, pull-up and pull-down are devices and power is only dissipated when both are on (if you ignore leakage, which is now significant).

 

So all SMT/SMD IC chips and circuit boards that are powered by 3.3volts are Nmos and Pmos not cmos?

No, CMOS is the primary technology now. NMOS and PMOS were abandoned because CMOS was lower power. If you look at any manufacturer that's been around for 40 years, they started with either NMOS or PMOS, depending on the substrate they used. CMOS was a natural evolution from NMOS or PMOS only. It was once thought that CMOS had too many processing steps, but now manufacturers deal with dozens of steps without batting an eye.

 

No, CMOS is the primary technology now. NMOS and PMOS were abandoned because CMOS was lower power.

So SMT/SMD IC components are CMOS, but it's a new type of CMOS that operates at 3.3volts? which type of CMOS is this? since they changed the new CMOS threshold limits

NMOS and PMOS draw to much current, NMOS and PMOS has to much leakage, NMOS and PMOS EEPROM chips didn't retain memory for long period of time.

 

So SMT/SMD IC components are CMOS, but it's a new type of CMOS that operates at 3.3volts? which type of CMOS is this? since they changed the new CMOS threshold limits

NMOS is still NMOS, PMOS is still PMOS, and CMOS is still CMOS. You don't change the fundamental device when you change the threshold voltages. Even when you're talking about techniques used to improve drive current on short channel devices, the basic device is the same.

NMOS and PMOS draw to much current, NMOS and PMOS has to much leakage, NMOS and PMOS EEPROM chips didn't retain memory for long period of time.

Where do you get that notion? The storage element in most (maybe all, I'm only familiar with a few companies) is an NMOS transistor with a floating gate. Charge is stored on the gate to change the threshold voltage of the device (see a common thread here?).

 

NMOS is still NMOS, PMOS is still PMOS, and CMOS is still CMOS. You don't change the fundamental device when you change the threshold voltages. Even when you're talking about techniques used to improve drive current on short channel devices, the basic device is the same.

They are using CMOS still but only changed the threshold voltage down lower because the clock frequency with up?

When lowering the power down to 3.3 volts it's more sensitive to EMI, noises and other interferences

 

They are using CMOS still but only changed the threshold voltage down lower because the clock frequency with up?

When lowering the power down to 3.3 volts it's more sensitive to EMI, noises and other interferences

Yes, but you can still work with it pretty well since things take much less space that way, and so is also more easily shieldable due to its compactness. You can also work at much higher frequencies because it will dissipate less EMI from the PCBs traces itself.

 

I would think compact very close traces at high frequencies is capacitive coupling. That is why when I have a SMT/SMD logic board powered on and move my electric screwdriver or drill over the logic signals it causes glitches and errors. This doesn't happen with TTL or CMOS circuits from the 70's or 80's any reason why?

 

I would think compact very close traces at high frequencies is capacitive coupling. That is why when I have a SMT/SMD logic board powered on and move my electric screwdriver or drill over the logic signals it causes glitches and errors. This doesn't happen with TTL or CMOS circuits from the 70's or 80's any reason why?

Do you use 4-layer PCBs with ground and power planes?

 

Do you use 4-layer PCBs with ground and power planes?

No Why? its just double layer SMT not a multi- layer at all

Why would multi-layers boards be more sensitive to RFI/EMI or interfaces?

 

Why would multi-layers boards be more sensitive to RFI/EMI or interfaces?

Ground planes can be used to shield critical signals. That technique is commonly used in the design of microprocessors. Critical signals are routed close to power supplies both for shielding and to reduce the effect of crosscap.

 

Ground planes can be used to shield critical signals. That technique is commonly used in the design of microprocessors. Critical signals are routed close to power supplies both for shielding and to reduce the effect of crosscap.

That was my point, exactly.