new logic boards use 3.3 volts. why don't they use 5 volts anymore and use 3.3volts? I would think you would get more current when using 5 volts which can drive more IC chips compared to 3.3volts. Is this Cmos or what type of Cmos family uses 3.3vds and not 5 volts?

 

I suspect batteries have something to do with it. A really old logic standard, RTL, used 3.3 V, but it was discontinued in the 70's.

 

All SMT/SMD circuit boards now use 3.3volts. But I'm not sure what type of CMOS family it is or why they would change the standardization to 3.3volts instead of using 5 volts. Any advantages?

 

why don't they use 5 volts anymore and use 3.3volts?

Power dissipation.

 

The lower voltage levels are due to power dissipation with a term proportional to Vcc squared as the signals beat up and down faster. Inside the largest chips the voltages are even lower. See page 4 of the following paper.
http://www.ti.com/lit/an/scaa035b/scaa035b.pdf

 

Yes they use the lower voltage at 3.3 volts to have less power dissipating and use less wattage rates on the components. But couldn't they have done this with TLL and CMOS 30years ago? The TTL and Cmos logic signals were +5 volts for a reason and now they are 3.3volts.

 

I personally try to avoid 3.3V technology in my projects, since it's very distance-sensitive when assembled in a PCB, it's also more prone to be affected by EMI and therefore needs good shielding practices. But sometimes parts are available only in that technology.
On the other hand, as Bill just said, it also consumes less power, and is more efficient and less prone to produce heat, as Papabravo just mentioned.

 

Yes they use the lower voltage at 3.3 volts to have less power dissipating and use less wattage rates on the components. But couldn't they have done this with TLL and CMOS 30years ago? The TTL and Cmos logic signals were +5 volts for a reason and now they are 3.3volts.

Keep in mind the original TTL technology was very inefficient, and was quickly superseded by TTL-LS, which consumes less power.

 

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Yes they use the lower voltage at 3.3 volts to have less power dissipating and use less wattage rates on the components. But couldn't they have done this with TLL and CMOS 30years ago? The TTL and Cmos logic signals were +5 volts for a reason and now they are 3.3volts.

Voltage wasn't lowered until power dissipation became an issue. Then manufacturers had incentive to lower the threshold voltage for CMOS devices. Internally logic runs at around 1V (now). They have very low power states where logic will maintain state, but can't operate. Within a processor, blocks of logic that aren't being used are placed in low power states. Cores that aren't being used are also put in lower power states and clock frequency is scaled back under light load.

It's all about power; as frequency went up, dynamic power dissipation went through the roof. That's why microprocessor wars stopped being about who had the highest clock frequency. Then device leakage because a factor and manufacturers started introducing high Vt devices for low power and low Vt for performance (within microprocessors/SoC's).

 

This is a good read, and will probably complement the answer to your original question much better:

Low-power Schottky TTL (LS) – used the higher resistance values of low-power TTL and the Schottky diodes to provide a good combination of speed (9.5ns) and reduced power consumption (2 mW), and PDP of about 20 pJ. Probably the most common type of TTL, these were used as glue logic in microcomputers, essentially replacing the former H, L, and S sub-families.

http://en.wikipedia.org/wiki/Transistor–transistor_logic

 

Yes they use the lower voltage at 3.3 volts to have less power dissipating and use less wattage rates on the components. But couldn't they have done this with TLL and CMOS 30years ago? The TTL and Cmos logic signals were +5 volts for a reason and now they are 3.3volts.

No. 50 years ago they did not know how to make high density semiconductors with small feature sizes. TTL and it's predecessors RTL and DTL were around for 10 years before commercial CMOS chips showed up. CMOS is what made things happen and it did not show up until 1972-73. 5 volt logic had to have some margin and some noise immunity and if you look at the TTL thresholds you realize the very few gates actually swung between GND and +5V.

 

I personally try to avoid 3.3V technology in my projects, since it's very distance-sensitive when assembled in a PCB, it's also more prone to be affected by EMI and therefore needs good shielding practices.

I have noticed this problem also, why is using 3.3volts more sensitive to outside interfaces? When I have a circuit powered on I put my electric screwdrivers or drill over the logic chips and it will cause glitches and logic errors. TTL and CMOS never had this problem i think

t's all about power; as frequency went up, dynamic power dissipation went through the roof.

So when the clock frequency got higher the logic chips don't need more power or voltage?

Why can't i just turn the voltage down from 5+ volts to 3.3volts on a TTL or CMOS logic circuit from the 70's and 80's?

 

5 volt logic had to have some margin and some noise immunity and if you look at the TTL thresholds

Right, but why did they standardize the TTL and CMOS thresholds to those values? and now they just changed the thresholds, we could have changed the threshold values 30yrs ago and turned the voltage down to 3.3volts 30yrs ago. They set the thresholds for a reason. Noise Immunity can be cleaned up the logic power rails by using a switching power supply, but a switch power supply can cause noise immunity switching and noises also.

 

CMOS thresholds have always been set at Vcc/2. TTL thresholds are set at [0.8, 2.4] because of the nature of the multi-emitter transistors used. I guess it's easy for you to say in hindsight what should have been done, but you weren't there Charlie, and you have no freaking idea what the giants, whose shoulders we stood on, accomplished. You just might want to be a bit more respectful.

They standardized those values so engineers all over the world could use them with confidence.

 

So when the clock frequency got higher the logic chips don't need more power or voltage?

Dynamic power in logic is a function of frequency, voltage, and capacitance (CMOS). If you increase frequency but lower operating voltage, power doesn't need to increase.

Why can't i just turn the voltage down from 5+ volts to 3.3volts on a TTL or CMOS logic circuit from the 70's and 80's?

Threshold voltages.

The move to 3.3V started around the Pentium II generation. Chips were running internally at 3.3V (for power dissipation), but had to have high voltage I/O. It made more sense for the ecosystem to be 3.3V. But processors continued to decrease operating voltage. Other logic can't run at those 1.8V or lower because parasitics can't be controlled as well as within the processor.

 

CMOS is what made things happen and it did not show up until 1972-73.

CMOS wasn't always a favored, or even promising, technology for some. Intel stayed with NMOS and PMOS only designs for years because latch-up was such a severe problem. If you look at the 4xxx CMOS family, it maxes out way below TTL. No one was thinking that CMOS could run at 5GHz and TTL (even ECL) can't compete.

 

If you increase frequency but lower operating voltage, power doesn't need to increase.

I don't get it, ohms laws doesn't say that when frequency goes up power wattage goes down

CMOS thresholds have always been set at Vcc/2. TTL thresholds are set at [0.8, 2.4] because of the nature of the multi-emitter transistors used.

What do they use now so they can use 3.3 volts?

Multi emitter transistor could have been biased to be tripped at 3.3 volts

 

I don't get it, ohms laws doesn't say that when frequency goes up power wattage goes down

Ohm's Law doesn't deal with frequency or capacitance. And you're wrong anyway. Dynamic power is a function of capacitance, voltage, and frequency. If frequency goes up and capacitance and voltage remain constant, power dissipation has to increase. If you make an offsetting change to one quantity, power doesn't have to go up.

What do they use now so they can use 3.3 volts?

As I've mentioned in just about every one of my posts; they changed threshold voltages of the NMOS and PMOS devices.

Multi emitter transistor could have been biased to be tripped at 3.3 volts

Either you are a lot smarter than the millions of people working in the semiconductor design industry, or you just have the benefit of research done by them. When I worked in the industry, what we were doing wasn't in text books. Some of the things I worked on won't be in text books for years after it's released from trade secret protections.

 

Oh so it's NMOS and PMOS devices not CMOS anymore?

They used NMOS and PMOS back in the 80's. They made us change all the NMOS and PMOS EEPROM chips to CMOS EEPROM chips because of latching problems and power was less using CMOS EEPROM chips.

The first Z80 was NMOS and it caused errors of latching problems and would draw to much current.

 

CMOS wasn't always a favored, or even promising, technology for some. Intel stayed with NMOS and PMOS only designs for years because latch-up was such a severe problem. If you look at the 4xxx CMOS family, it maxes out way below TTL. No one was thinking that CMOS could run at 5GHz and TTL (even ECL) can't compete.

I disagree. We always knew that CMOS would eventually win because because the power dissipation problems limited every other technological competitor. Reducing the feature size while increasing the wafersize was evident by the early 1980's. We also knew there was a successor to visible light lithography.