Hi everyone,

I would like to know if someone knows why the current in the second stage of a two-stage opamp, has to be bigger than the first stage?
What happens if the current in the second stage is bigger than the first?

Best regards.

 

Depends upon the design, which we have no idea what that is.

 

If it is power amplifier, then first stage amplifies voltage, second stage amplifies current, the total effect is power amplifier because Power=V*I.

 

Hi, the amplifier is a 2 stage OpAmp with Miller compensation.

Regards

 

Be kind and take the pain of showing a complete schematic.

 

Hi, the amplifier is a 2 stage OpAmp with Miller compensation.

Regards

There are two poles and one zero. To make it stable and get the desired phase margin, you should seperate the second pole and zero far from the origin for a specific phase margin.

 

amplifier is a 2 stage OpAmp with Miller compensation.

In a bipolar amplifier, one of the reasons is to keep current low in the first stage to reduce input bias currents.

 

In a bipolar amplifier, one of the reasons is to keep current low in the first stage to reduce input bias currents.

How did we get from op amp to bjt?

 

How did we get from op amp to bjt?

Many opamps have bipolar inputs, some have JFET/etc. OP isn't talking about specific opamps, so I offered a general comment on bipolar opamps. Capiche?

 

Sorry for causing all of this misunderstanding.

I could put a picture but it is a simple 2 stage opamp, miller compensation, using MOSFETs and say pmos input pair.

Just one comment about anhnha response.
I have thought about that, because the gm in the second stage define the second pole, so bigger current bigger gm bigger bw.

Now let analyse it from slew rate perspective. Same question but now supposing that the opamp is slewing. What are the differences?

 

Sorry for causing all of this misunderstanding.

I could put a picture but it is a simple 2 stage opamp, miller compensation, using MOSFETs and say pmos input pair.

Just one comment about anhnha response.
I have thought about that, because the gm in the second stage define the second pole, so bigger current bigger gm bigger bw.

Now let analyse it from slew rate perspective. Same question but now supposing that the opamp is slewing. What are the differences?

Please include schematic. Even if some of the experts here can answer your question based on your sparse description, less experienced people, like me, who are still learning will benefit greatly from seeing the schematic while reading the discussion. Thanks!

 

Please include schematic. Even if some of the experts here can answer your question based on your sparse description, less experienced people, like me, who are still learning will benefit greatly from seeing the schematic while reading the discussion. Thanks!

I believe it is secret and covered by NDA.

 

I believe it is secret and covered by NDA.

I thought that one if the goals of open, public forums like this was for everyone to be able to learn from the discussions, not just for a few individuals to get private consultations.

If the question is so specific to a unique, proprietary circuit that the schematic can't be shared, it seems like it couldn't be answered without that schematic.

On the other hand, if the question refers to common, well-known arrangements, then generic representations of that circuit should suffice.

Is the circuit in question something like these?

 

Sorry for causing all of this misunderstanding.

I could put a picture but it is a simple 2 stage opamp, miller compensation, using MOSFETs and say pmos input pair.
...

...
Is the circuit in question something like these?
View attachment 130447 View attachment 130448

This is the circuit from AMSA's description:

 

1. An output stage using a current generator can not give more current than the current generator.
2. There is a property of FETs: greater voltage gain at lower currents (for high-resistance loads such as a current generator). This can easily be shown for the simplest model of a transistor:
Id = B * (Vgs-Vto) ^ 2 ==> S = (d Id / d Vgs) = (Id) '= 2 * B * (Vgs-Vto) = 2 * sqrt (B * Id)
Rout = 1 / (Lambda * Id)
Gain_max = S * Rout = 2 * sqrt (B * Id) / (Lambda * Id) = 2 * sqrt (B) / (Lambda * sqrt (Id))
In fact, it is necessary to reduce the current density of the transistors of the first stage of the amplifier. And this is done in two ways: reducing the current or increasing the size of the input transistors. The second method is used to reduce noise.
I will make a note on the use of formulas.
They cease to be true in the subthreshold mode of transistors. Those. To obtain a high gain, it is necessary to use a subthreshold mode.