you haven’t much imagination.

Does you imagination include the expertise needed to program your "optimal" solution?

 

How do I do that? Can I use transistors with their bases connected to the main supply to disconnect each output from GND when the power is off?

If the outputs are going to CMOS inputs, then you could add a large resistor (say 1meg) in series with each output to minimize the battery current draw when the circuit power is off.

Alternately you could use a tri-state buffer (e.g. CD4503) at the outputs, powered from the battery, which is put in the tri-state mode when the power is removed.
The outputs are then open-circuit.

 

How much glue logic do you think it would take to convert addresses and data from parallel to serial and back? Seriously...

I'm trying to design a 1-bit EEPROM

Where did the requirement for addresses and serial to parallel come from?

Bob

 

Does you imagination include the expertise needed to program your "optimal" solution?

Yes, mine certainly does.

Bob

 

Where did the requirement for addresses and serial to parallel come from?

First sentence from the OP.

I'm trying to design a 1-bit EEPROM with the ultimate goal of designing a 4x4 bit EEPROM.

 

I'm not sure about using 2N7000s, how about 4051s?

https://www.ti.com/lit/ds/symlink/cd4051b.pdf

This is a CMOS single 8 channel analog multiplexer/demultiplexer
made with transmission gates.

https://en.wikipedia.org/wiki/Transmission_gate

If you hang a capacitor off of each of the 8 channel pins you can
interrogate and set each capacitor (one at a time) from the common pin.

I think you will still need a battery to keep the 4051 powered up at all
times -- I suspect if the 4051 loses power the likely protection diodes
to power and gnd on the capacitor pins will discharge your capacitors.

Also the 4051 needs to be in inhibit mode when the rest of the circut
doesn't have power. This is a problem as the inhibit line needs to
be high to inhibit the 4051 and keep all the transmision gates off.
A simple resistor to the battery keeping the 4051 on won't work as the
outside powered down circuit will sink current from the battery through
the resistor.

The low power way to drive the inhibit line takes a CMOS inverter also
on battery power. Then the inverter input can go low when whatever
driving it is powered off with no sneek battery path leakage.

For 16 bits you need two 4051s and capacitors along with a bit of decoding
logic to pick which to enable. Likely the CMOS "inverter" can really
be something like a 74HC00 (4 NANDs) to both invert the inhibit lines
and control which 4051 gets enabled/inhibited (or both inhibited for
power off).

https://media.digikey.com/pdf/Data Sheets/ON Semiconductor PDFs/74HC00.pdf

 

Yes, mine certainly does.

Bob

Good, since you micro guys tend to dismiss the complexity of learning how to program, which is not trivial as some imply.

 

Mea culpa.

I don’t know how I missed that was reading too much into the title.

I would then use a low end 14 pin PIC for a few cents more.

Bob

 

Thanks for your reply. Do I need the Schottky diode if the coin cell is only powering the CD4099 and the main power supply is powering the rest of the circuit? Ie. The main power supply won't power the CD4099.

My understanding is that I need the Schottky to isolate the battery if the battery was powering the whole circuit, and, therefore, conflicting with the main power supply. Perhaps I'm wrong.

Unfortunately, CD4099 doesn't have tri-state outputs, so you'll need more than a diode. If the outputs drive any CMOS inputs, the input protection diodes will power up the positive rail and discharge the battery.

 

If the outputs are going to CMOS inputs, then you could add a large resistor (say 1meg) in series with each output to minimize the battery current draw when the circuit power is off.

3 volts across 1 meg results in 3uA when power is off. That's huge compared to CMOS non-switching power/current levels.
Try using a transfer gate (4066 concept) to disconnect the outputs.

https://www.ti.com/lit/ds/symlink/cd4066b.pdf

 

If the outputs are going to CMOS inputs, then you could add a large resistor (say 1meg) in series with each output to minimize the battery current draw when the circuit power is off.

Alternately you could use a tri-state buffer (e.g. CD4503) at the outputs, powered from the battery, which is put in the tri-state mode when the power is removed.
The outputs are then open-circuit.

Thanks for your help. I'll order everything I need, and report back!

 

I'm not sure about using 2N7000s, how about 4051s?

https://www.ti.com/lit/ds/symlink/cd4051b.pdf

This is a CMOS single 8 channel analog multiplexer/demultiplexer
made with transmission gates.

https://en.wikipedia.org/wiki/Transmission_gate

If you hang a capacitor off of each of the 8 channel pins you can
interrogate and set each capacitor (one at a time) from the common pin.

I think you will still need a battery to keep the 4051 powered up at all
times -- I suspect if the 4051 loses power the likely protection diodes
to power and gnd on the capacitor pins will discharge your capacitors.

Also the 4051 needs to be in inhibit mode when the rest of the circut
doesn't have power. This is a problem as the inhibit line needs to
be high to inhibit the 4051 and keep all the transmision gates off.
A simple resistor to the battery keeping the 4051 on won't work as the
outside powered down circuit will sink current from the battery through
the resistor.

The low power way to drive the inhibit line takes a CMOS inverter also
on battery power. Then the inverter input can go low when whatever
driving it is powered off with no sneek battery path leakage.

For 16 bits you need two 4051s and capacitors along with a bit of decoding
logic to pick which to enable. Likely the CMOS "inverter" can really
be something like a 74HC00 (4 NANDs) to both invert the inhibit lines
and control which 4051 gets enabled/inhibited (or both inhibited for
power off).

https://media.digikey.com/pdf/Data Sheets/ON Semiconductor PDFs/74HC00.pdf

Thanks for your reply. I'll order everything I need to implement the solutions suggested and report back.

 

Unfortunately, CD4099 doesn't have tri-state outputs, so you'll need more than a diode. If the outputs drive any CMOS inputs, the input protection diodes will power up the positive rail and discharge the battery.

The outputs do drive CMOS inputs. So, use diodes in between or not? Thanks!

 

Mea culpa.

I don’t know how I missed that was reading too much into the title.

I would then use a low end 14 pin PIC for a few cents more.

Bob

Thanks for your reply. My only purpose is to learn. I wanted to do the "custom EEPROM" just for the heck of it, and now I'm learning about adding a backup battery to my circuit. As I said, this is part of a bigger project. A PIC could actually do the work of the whole project, but my goal is to learn how to implement the whole thing without a microcontroller.

 

The outputs do drive CMOS inputs. So, use diodes in between or not? Thanks!

Use tri-state buffers on the outputs of the of whatever you use for the memory element. CD4503 was suggested; you'll have two unused buffers that have a separate enable.

 

whats wrong with just using an EEPROM

https://www.digikey.co.uk/product-d...logy/AT28BV64B-20JU/AT28BV64B-20JU-ND/1008568

 

whats wrong with just using an EEPROM

He felt it didn't make sense:

For instance, it doesn't make any sense to use a 28C16 if I'm only using 16 bits.

Using that logic, using a 64Kbit memory would make even less sense.

 

To me its a matter of cost / performance / reliability / size / documentation.

If an off the shelf part is as cheap as this, and well supported as this , and I'd say less cost than the designs your proposing,
why not use it ?

Its just a matter of where your priorities are,

if the requirement is a school project , which says make your own, then the answer might be different to a production enviroment,

 

I'm trying to design a 1-bit EEPROM with the ultimate goal of designing a 4x4 bit EEPROM. I need it for a bigger project, and I feel I would be wasting the full potential of a commercial EEPROM if I were to use one. For instance, it doesn't make any sense to use a 28C16 if I'm only using 16 bits. I'm using the 2N7000 MOSFET.

What you have actually done with your single 2N7000 is made a 1-bit DRAM (dynamic RAM). The gate charge leaks away and has to be regularly refreshed.

How do I design a memory cell that works as a real EEPROM? That is, it keeps the output status after power down forever.

An EEPROM does not keep its state forever - just quite a long time (50 years+).

I think magnetic is the way to go: A latching relay?