YABC (Yet Another Binary Clock) Project

Thread Starter

Lehthanis

Joined Dec 30, 2011
33
praondevou, is this what you're referring to regarding the diodes and pull up (attached). If not, then yes, if you coudl draw something up this evening, that would be awesome.

In this schematic, I'm not sure I understand what would prevent either Q4 or Q5 from going high and resetting IC4 as opposed to requiring BOTH Q4 and Q5 going high for the reset.

As for the schematic, I'm just using the symbols from Eagle's library...I didn't draw the counters themselves.

I'm not sure what bwack is referring to though :(

EDIT: I updated the pdf to fix the output of IC5B. Redownload if you downloaded it before this edit.
 

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bwack

Joined Nov 15, 2011
113
Yes, but what I'm concerned about and don't like is that the voltage on the reset pin is at the threshold when it changes, the value may be undefined and one can't rely on what happens on the outputs of the counter.

Here is my suggestion adding the 4013 back into the schematic, not for frequency dividing, but for shaping the reset/trigger pulses and also syncing them with the clock, and third I also see that any glitches on the ripple counter will be ignored because it will happen between clock cycles. (it also has to be added for hours and minutes too, but not shown in my drawing). I used the diagram that wookie edited http://forum.allaboutcircuits.com/showpost.php?p=438914&postcount=14
 

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Lehthanis

Joined Dec 30, 2011
33
Updated the attachment in my previous post. I like where you're goign with that bwack. I do want to take it one thing at a time though...Lets get through the 2 Input AND gate from IC4, then I'll come back to the glitches. I kinda have the solved, but you may be right about the timing and accuracy of it.
 

praondevou

Joined Jul 9, 2011
2,942
Here is my suggestion adding the 4013 back into the schematic,
That will give a defined pulse width of a few 100us for reset and enough HIGH time for the clock of the next counter, yes.

praondevou, is this what you're referring to regarding the diodes and pull up (attached).

In this schematic, I'm not sure I understand what would prevent either Q4 or Q5 from going high and resetting IC4 as opposed to requiring BOTH Q4 and Q5 going high for the reset.
Yes, that's what I meant. Both Q4 and Q5 need to be HIGH in order to get a HIGH on the reset input. With only one Q HIGH the RESET input will be pulled LOW through the other diode which is connected to the Q that is LOW.
 

praondevou

Joined Jul 9, 2011
2,942
Sweet, can you tell me how you calculated the value of the pull up resistor? I need to learn more about that.
I didn't. A wide range of resistor values will work in this case.
The higher the value the more sensible a circuit gets to noise pickup. The lower the more current flows (into the Q outputs in this case).
 

Thread Starter

Lehthanis

Joined Dec 30, 2011
33
I think I understand. Well, I'm going to pick up a couple of 4013's, some 1n4148's, a few more resistors, and try to make the version I've got here. After I get that working, I'll move on to some accuracy. Thanks much for all the help.

I do have a question though. Resistor wattages. I've been trying for 1/8 Watt resistors because that's what I calculated the wattage at for the LED's. Is that correct for the whole circuit, or just the LED's? How do I know what wattage of resistor to look for?
 

Thread Starter

Lehthanis

Joined Dec 30, 2011
33
The main reason I wanted to divide the 4060 pin 3 output into 1Hz is so the driving signal would be the same for all three 7-bit counters.

Without the 4013 dividing the signal, I'm having to skip the first bit of the seconds counter. Which means when I press the seconds button, the seconds advance much slower than minutes or hours when trying to set the clock. It basically offends my mild OCD. If you knwo of any other easier ways around that, I'm all ears.

I still like the idea of increasing accuracy on the 4082 triggering though...can we discuss that a little more? I know I could just "do it" based on the drawing you posted, but I don't quite get it...I want to understand too...thats what this project is about for me. ;)
 

bwack

Joined Nov 15, 2011
113
The main reason I wanted to divide the 4060 pin 3 output into 1Hz is so the driving signal would be the same for all three 7-bit counters.

Without the 4013 dividing the signal, I'm having to skip the first bit of the seconds counter. Which means when I press the seconds button, the seconds advance much slower than minutes or hours when trying to set the clock. It basically offends my mild OCD. If you knwo of any other easier ways around that, I'm all ears.
I have a good friend with OCD. His condition makes it hard to sleep at night. I understand now. It makes sence that the seconds will be half the speed when pushing to seconds button. Then you could use the 4Hz signal for the seconds? But I see now that you would need to press the seconds button up to two times to get a change in seconds wich is not good (depending on what Q1 was to begin with), that would make the seconds button kinda flimsy.

I still like the idea of increasing accuracy on the 4082 triggering though...can we discuss that a little more? I know I could just "do it" based on the drawing you posted, but I don't quite get it...I want to understand too...thats what this project is about for me. ;)
We could discuss it and try to draw some timing diagrams to see what is happening on the timescale. :)
 

Thread Starter

Lehthanis

Joined Dec 30, 2011
33
Is there a simpler, non-IC method of dividing the 2Hz into a 1Hz? I've successfully eliminated one of the 4082's with two diodes and a resistor...If I can eliminate the 4013 and do it with some smaller components, that'd be great. How many components are in a simple D flip flop?
 

bwack

Joined Nov 15, 2011
113
With RC network, if the time constant is much slower than the time for the counter and AND-gate to react (propagation delays), then the capacitor only charges to the threshold and starts to discharge right back into the forbidden region (voltage level between high and low thresholds of the reset pin is the forbidden region, then operation becomes uncertain).

When you removed the capacitor, this problem was solved, but then it would be ic-package dependend on how good the timing is. I've looked at propagation delays for two components running at 5V. http://www.nxp.com/documents/data_sheet/HEF4082B.pdf
and
http://www.nxp.com/documents/data_sheet/HEF4024B.pdf
Check for propagation delays (time until the output changes when inputs change) for both packages. If you sum those times together you get the pulsewidth of the and-gate output I think. I get it to be greater than the minimum required 40ns pulsewidth for the MR (reset) input as adverticed in the datasheet for the 4024. Thats probably why it works for you. And then there is also a pulsewidth requirement for the next 4024 clock input. Seems to be ok too for these two components. If you now select other brands or models of these devices, you will have to recheck the datasheet for propagation delay.
This is only one of the problems though, since you are interfacing a clock/reset input with a ripple counter, you must be aware of glitches during transitions (the transitions "ripple" through the internal d flip-flops). There might be a glitch when the inputs of the AND-gate transitions from 1101 to 1110 ? will there be a brief moment when inputs are 1111 durring this transition in question? I don't think there is... If anyone can explain this better it would be nice.

All of these problems would be eliminated by a simple d flip-flop for each AND-gate syncronized with the clock. This is very common in larger digital designs too, for example in CPLDs and FPGAs.
This is helpful is because you leave time for the logic gates to stabilize their final result before bringing it to whoever needs it. You get get many flipflops in one package, actualy you could get the quad flipflop package, then you have one for the 2Hz to 1Hz signal and three for the reset and clock inputs. The hex inverter one is also good but it doesn't have the negative Q output required for 2Hz to 1Hz signal, but you could invert the Q signal fed back to the flipflop with a transistor and resistors?
Anyways just some ideas.
 

Thread Starter

Lehthanis

Joined Dec 30, 2011
33
Interesting!

So, I'm attaching a schematic that I think roughly captures what you're referring to using a 4175. I'm not sure if I've got it set up for the right inputs and outputs, and I'm also not sure if the values for R19, R20, R24, R31, and R25 are still valid or even necessary.

I'm also not sure if I need to tie IC2's Q01, Q02, and Q03 to something. Whatcha think?

Edit: BTW I'm using the motorola packages...MC14082B and MC14024BCP.
 

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Lehthanis

Joined Dec 30, 2011
33
praondevou, I just built Binary Clock 3 (http://forum.allaboutcircuits.com/showpost.php?p=440338&postcount=21) and it seems to work like a champ! The 1n4148's worked perfectly for removing one of the 4082's. The 4013 is working great for dividing my clock to 1Hz, and now the seconds change just as fast as minutes and hours...everything seems to count properly and reset properly.

I bought a 4175 in order to try v4 above...but I wanted someone to look at it first. This is so awesome, thanks for all the help everyone!
 

bwack

Joined Nov 15, 2011
113
Interesting!

So, I'm attaching a schematic that I think roughly captures what you're referring to using a 4175. I'm not sure if I've got it set up for the right inputs and outputs, and I'm also not sure if the values for R19, R20, R24, R31, and R25 are still valid or even necessary.

I'm also not sure if I need to tie IC2's Q01, Q02, and Q03 to something. Whatcha think?

Edit: BTW I'm using the motorola packages...MC14082B and MC14024BCP.
Thanks for the new schematics (v4). It looks ok. No you don't have to tie unused outputs (Q01, Q02 etc), it is important to tie unused inputs to Vss or Vdd, or else the outputs can start screaming at high frequencies, causing massive noise. All inputs are used on IC2 in the schematics v4.

Lets look at the signals. I was abit worried about loosing a count with this setup of the 40175 (4175?), but thinking of it, the flipflop is running at 2Hz, the counter at 1Hz..



Look here how the counter only changes when 1Hz_CLK is going low, and the flip flop Q1 (IC2) changes its output when 2Hz_CLK goes High.. I see now that It was unfortunate to include the 2Hz-1Hz signal in this package. It doesn't look like you are loosing any counts (Edit: but we are, see discussion below), but you see that the value 60 is held for 0.5s then 0 is held for 0.5s. Originally I was hoping the clk input of this flipflop was tied to a much higher frequency, that would help alot, but then you can't use this device to divide the 2Hz frequency to 1Hz.
Always draw a timing diagram like this, starting with the clock inputs.
Edit. hmm, looks like if the 2Hz is used as clock, there is another problem that the flip flop Q1 will be held for too long and you actually are loosing a count because when the next count is comming, the reset signal is still high. For this to work you need to attach the clock input of this flipflop to a higher frequency. I don't want to redraw that schematic :)
 
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Thread Starter

Lehthanis

Joined Dec 30, 2011
33
So, should I leave it at version 3 or do you think there's a way to make it work with the 4175? I think I see what you're saying, but you also make it sound like there's a workaround?
 
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