I got this "interesting" one wire bus here:
The problem I have is I am working on a slave side.The master will generate a clock. When the bus is idle. The master will put 8 bit of 0 on the bus.
eg: sync -> 0b000 00000 -> sync -> 0b0000 0000 ... etc
If a slave want to put a 1 on the bus, the slave has too pull the bus high at 1/2 cycle to make it bit 1, it's bit like a one wire bus, but not a one wire bus.
Any input is appreciated!
Thanks guys!

- Every byte start with a sync "signal"
- The duration of this sync signal is 4 bits long. (2 bits low and follows by 2 bits high)
- bit 1 is 1/2 cycle low and 1/2 cycle high
- bit 0 is 3/4 cycle low and 1/4 cycle high
The problem I have is I am working on a slave side.The master will generate a clock. When the bus is idle. The master will put 8 bit of 0 on the bus.
eg: sync -> 0b000 00000 -> sync -> 0b0000 0000 ... etc
If a slave want to put a 1 on the bus, the slave has too pull the bus high at 1/2 cycle to make it bit 1, it's bit like a one wire bus, but not a one wire bus.
Any input is appreciated!
Thanks guys!
