Write data in this "interesting" one wire bus

Discussion in 'General Electronics Chat' started by bug13, Mar 23, 2016.

  1. bug13

    Thread Starter Senior Member

    Feb 13, 2012
    I got this "interesting" one wire bus here:

    • Every byte start with a sync "signal"
    • The duration of this sync signal is 4 bits long. (2 bits low and follows by 2 bits high)
    • bit 1 is 1/2 cycle low and 1/2 cycle high
    • bit 0 is 3/4 cycle low and 1/4 cycle high
    I have no problem reading the data out, with the help of a input capture module of a pic. But now I want to write some data in the bus.

    The problem I have is I am working on a slave side.The master will generate a clock. When the bus is idle. The master will put 8 bit of 0 on the bus.
    eg: sync -> 0b000 00000 -> sync -> 0b0000 0000 ... etc

    If a slave want to put a 1 on the bus, the slave has too pull the bus high at 1/2 cycle to make it bit 1, it's bit like a one wire bus, but not a one wire bus.

    Any input is appreciated!

    Thanks guys!

  2. WBahn


    Mar 31, 2012
    Is your diagram to scale? You talk about the sync length in bits and say that it is two LO bits followed by two HI bits. But then you talk about bits in terms of cycles.

    If it takes 4 time units to transmit the sync signal, how many time units does it take to transmit each data bit?

    I have no idea how to interpret, "it's bit like a one wire bus, but not a one wire bus."

    When you say that the master will put eight 1 bits on the bus, is that eight 1 bits in the same vein as the data bits? That's my guess.

    Does the master drive the bus LO and HI, or does it just drive it HI and it is pulled passively LO? If the latter, then your slave can drive it HI. It just has to monitor the bus in order to know when the mid-point is.

    My question is how can the slave know that the frame it is seeing is an idle frame that it can override versus a real frame of data that it should be reading?
  3. bug13

    Thread Starter Senior Member

    Feb 13, 2012
    Sorry I diagram is not draw to scale.
    Let me say what I mean in another way:
    • sync length is 4 unit time, two low and two high
    • one bit is 1 unit time, both bit_zero and bit_one have 1 unit time
    • bit_zero is 3/4 unit time low and 1/4 unit time high
    • bit_one is 1/2 unit time low and 1/2 unit time high

    • each data bit is 1 unit time

    Sorry I don't understand what do you mean by "is that eight 1 bits in the same vein as the data bits?"

    The master drive the bus LO and HI, but the master has the ability to detect that a slave drive the bus high when the bus is actually LO (by detecting current). On detection, the master drives the bus high straight away.

    I guess I can poll the bus and detect the mid-point, but I don't want to use polling method. Because I don't think polling will work. I prefer an interrupt driven option, but I don't have a clue on how to detect a mid-point with interrupt.

    This is a good question.
    • A bigger number has higher priority than a smaller number, eg 0xFF has the highest priority, 0x00 has the lowest priority.
    • data is always transmitted MSB first.
    • so a bigger byte (in value) will always override a smaller byte (in value)
    • if two slave want to send different byte at the same time, they will also read the bus at the same time. If read back byte is different from what that slave put on the bus, that slave knows it has lower priority. That slave will resend the data on next sync signal
    • this priority detection is done on first byte follows by the sync signal

    Thank you for looking into this, and feel free to ask for more info if required.

    Thanks a lot!