So I was fooling around with a circuit simulator and I put a j-FET and n-FET opposing each other, with a NPN and PNP transistor on each side... it limited current to 2.6 A.


The circuit simulator:
https://tinyurl.com/2c3w48lo

I created two of them, with diodes so current doesn't flow backwards through each limiter, so that it can be used on AC. The circuit itself is just a full-wave rectifier and capacitive voltage divider used to charge a large capacitor bank (the bottom cap). That's not important.

Would the current limiter actually work like in the simulator, or would it just blow the FETs?

 

The schematic is unreadable, all bunched up? why?

 

What J-FET parameters did you use?

 

What J-FET parameters did you use?

The default for Falstad, threshhold voltage 4 or -4, beta 1.25m.

 

Here's a more exploded view, with potentiometers to adjust the regulated current (from ~106 mA to 2.6 A at maximum voltage):

https://tinyurl.com/2aolw4nm

But I'm still not sure if it'd actually work like that in a real circuit.

Right-click the resistors and select 'Sliders' to change the range of adjustment.

 

The circuit posted is an artistic drawing, but not very useful for understanding how a circuit functions. Black lines with a white background are quite good enough to be understood. Traditional symbols are quite the best choice. If we can read the circuit than many folks will see how it works, or is supposed to work.

 

I believe it is a simulation artifact, due to incomplete or erroneous models.
Also, under certain conditions, like high current limits, the JFET gates are conducting current. An anomalous condition on the real world.

But I would like to be proven wrong… can you provide an explanation how the circuit works?

 

I believe it is a simulation artifact, due to incomplete or erroneous models.
Also, under certain conditions, like high current limits, the JFET gates are conducting current. An anomalous condition on the real world.

But I would like to be proven wrong… can you provide an explanation how the circuit works?

I'm not really sure why it works like that... near as I can figure, the gate-to-source voltage vs. the drain-to-source voltage keeps the JFETs in a state of high resistance, which limits the amount of current the PNP transistor's base can shunt to the NPN transistor's base, thus limiting output current. And as input voltage changes, that ratio adjusts the JFET resistance such that the transistors limiting current keeps the output current steady (it actually rises by a tiny bit as input voltage rises... on the order of 0.02 amps).

But like I said, I'm not sure, nor am I sure it'd actually work like that in the real world. I don't have the setup to test it at the moment.

 

I'm not really sure why it works like that... near as I can figure, the gate-to-source voltage vs. the drain-to-source voltage keeps the JFETs in a state of high resistance, which limits the amount of current the PNP transistor's base can shunt to the NPN transistor's base, thus limiting output current. And as input voltage changes, that ratio adjusts the JFET resistance such that the transistors limiting current keeps the output current steady (it actually rises by a tiny bit as input voltage rises... on the order of 0.02 amps).

But like I said, I'm not sure, nor am I sure it'd actually work like that in the real world. I don't have the setup to test it at the moment.

You'll note in the circuit simulator that as input voltage rises, JFET gm (transconductance) goes lower.

Conductance is the reciprocal of resistance, so if r = 1/gm, as gm goes lower, resistance through the JFET goes higher. This keeps the amount of current flowing from the base of the PNP transistor (and to the base of the NPN transistor) at a relative constant even as input voltage increases. And it is the base current of the transistors which determines how much current they will pass, which determines output current.

That's how I came to the conclusion above. But I'm not sure if it's true, and need someone with more knowledge and experience to evaluate it.