Why is transmission gates not working properly in LTSpice?

Thread Starter

Ajith96

Joined Apr 4, 2020
7
I implemented a transmission gate with nmos and pmos in LTSpice. But it behaves like a short circuited wire on all conditions for nmos and pmos. I know what a MOSFET is and how it works and all. I ain't a newbie to LTSpice too. So please implement Transmission gates in LTSpice and then reply.
 

Papabravo

Joined Feb 24, 2006
13,551
I implemented a transmission gate with nmos and pmos in LTSpice. But it behaves like a short circuited wire on all conditions for nmos and pmos. I know what a MOSFET is and how it works and all. I ain't a newbie to LTSpice too. So please implement Transmission gates in LTSpice and then reply.
Operator error is the most likely explanation at the moment, without further evidence or information. Maybe you could show us what you have done so far and we might be able to offer helpful suggestions. Short of that we would be guessing.
 

Papabravo

Joined Feb 24, 2006
13,551
What are the parameters of the inverter A1? Output High? Threshold?
What are the thresholds and fully on parameters of the MOS transistors? It the 1V default output of the inverter enough to turn anything on or off?
Since Vg is set to 0, and is not changing, what did you expect to happen?
Is the library tsmc018.lib publically available?
 

Alec_t

Joined Sep 17, 2013
11,158
For future reference, please always post your asc file when discussing LTspice simulations.
N.B the default NMOS and PMOS device models rarely do what you want. Use real-device models instead.
 

Papabravo

Joined Feb 24, 2006
13,551
For future reference, please always post your asc file when discussing LTspice simulations.
N.B the default NMOS and PMOS device models rarely do what you want. Use real-device models instead.
The real device models are monolithic parts described in the tsmc018.lib library which I am guessing is proprietary.
 

Bordodynov

Joined May 20, 2015
2,561
You made two mistakes:
1. It is necessary to control this circuit with a full voltage range equal to the supply voltage. At 1 V p-channel transistor gate voltage, the transistor is open. The transistor must be fed into the 1.5 V gate to be closed.
2. You do not use a load (resistor) at the output of this circuit. Even if you correct the high output level of the logic element to 1.5 V, the output without the load resistor (no-load) will have a voltage slightly less than 1.5 V. This is due to the fact that the transistors have subthreshold current.
The situation can be changed by p-n junction currents, but it seems that you may not have specified the corresponding areas.
 
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Thread Starter

Ajith96

Joined Apr 4, 2020
7
I just used a built-in digital inverter. So no idea about the its parameter but getting the desired output from it.

Vth of MOSFET is given a 0.5V. Have attached the info about the MOSFET used.

Yes the 1V output of the inverter should be sufficient. Have use the same model in my other works like sample and hold circuits, worked like a charm.

Vg of NMOS is 0 and that of PMOS is 1, so it expect both the NMOS and PMOS to be in OFF state. But somehow it doen't work like that and thats the issue here.

I don't know about the availability of the library, i just got it from my seniors like 2 months back.

I have shared by asc file too. I just want to implement a transmission gate in my sample and hold circuit instead of a NMOS. Any library any method is ok with me. Because resistance of Transmission Gate is quite uniform wrt to vds.

Please do ask me incase u need anything more. Thanks
 

Attachments

Thread Starter

Ajith96

Joined Apr 4, 2020
7
You made two mistakes:
1. It is necessary to control this circuit with a full voltage range equal to the supply voltage. At 1 V p-channel transistor gate voltage, the transistor is open. The transistor must be fed into the 1.5 V gate to be closed.
2. You do not use a load (resistor) at the output of this circuit. Even if you correct the high output level of the logic element to 1.5 V, the output without the load resistor (no-load) will have a voltage slightly less than 1.5 V. This is due to the fact that the transistors have subthreshold current.
The situation can be changed by p-n junction currents, but it seems that you may not have specified the corresponding areas.
Hi,
1. Sorry about that. I understand that difference between gate and source voltage should be less that Vth inorder for the transistor to OFF. Eventhough if Vdd = Vg(PMOS) = 1 Volt, the T-Gate works like Closed switch.
2. Yes I do tried keeping a resistor in both the input and output of the T-Gate but the resistors too worked like a short circuited ones, not even a 0.1V drop across the resistor occured. I understand there is some problem here, kindly help me through it.
 

Bordodynov

Joined May 20, 2015
2,561
You have a very basic knowledge of LTspice and the properties of CMOS transistors. That's what I wrote about earlier. The leakage current of closed transistors is slightly less than one nanoampere.SwCMOS.png
 

Thread Starter

Ajith96

Joined Apr 4, 2020
7
You have a very basic knowledge of LTspice and the properties of CMOS transistors. That's what I wrote about earlier. The leakage current of closed transistors is slightly less than one nanoampere.View attachment 203466
Maybe i dont know much about LTSpice. But incase of MOSFET i dont think so. Are u saying subthreshold current in the order of nA is the reason for the transistor to work like a short circuited wire????

As I have told already, I tried the resistor part but had the same result.

Also would like to know how to change the parameter of the inverter like Vhigh and Vref.
 

Attachments

ci139

Joined Jul 11, 2016
1,376
a simplified model

pRAM - Test - b15q.png
Code:
* transmission/pass gate
* GND +CTRL IN OUT Vs
.SUBCKT PsGate 1 2 3 4 5
R0 3 4 R=Rch()+.1G*u(V(5,2)-V(2,1))
.param aa = 12k5
.param bb = -161m
.param cc = 110
.param dd = -2.1
.func Rch(){cc+aa*(V(5,1)+bb)**dd}
.ENDS
↑ you may want to adjust it to your needs (as the frequency bandwidth goes highest at about 50 to 100 MHz at 15V Vcc) ↑
or use voltage controlled switch http://ltwiki.org/index.php?title=S_Voltage_Controlled_Switch
 
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Thread Starter

Ajith96

Joined Apr 4, 2020
7
You made a mistake for beginners. When you copied, you copied a node label. All nodes with the same tag are connected to each other.View attachment 203575
Thanks. Corrected it, but still there is no voltage drop. Couldn't get what is the first graph is (The nanoAmpere graph).

Couldn't get the desired current characteristics, if the output terminal is not grounded. Why is that so?

Also earlier u have said that if there is some subthreshold conduction then the voltage drop will be very minimal. Have I misunderstood what u said?
 

Attachments

Bordodynov

Joined May 20, 2015
2,561
LTspice allows you to change axles. Click on the Y-axis and the menu will pop out! Make changes for the logarithmic scale.
I grounded the exit to find the maximum leakage. At higher voltages (>0V), there will be less leakage. As I said before, the closed transistor also has a leakage. In Spice programs there is a minimum conductivity (this value can be changed) look in HELP.
Why do you need such a switch? The switch switches the load. When there is no load, there is no switching. In reality, with such a circuit you will want to measure the output voltage (relative to ground) with a meter. The voltmeter has a resistance of 10 - 100 MegaOhm. Connect 20 MegaOhm between the output and the ground. See what voltage you get. You simulate reality in this way.
 
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