What form of compensation are you talking about here? Do you mean like a lead or lag network?

You'll have to specify a particular circuit here because it's not fair to generalize every buck circuit into an oscillator and then state that it oscillates. For example the buck plant is not an LC circuit, it's an RLC circuit, and even a RRLC circuit where we have at least two major resistances working inside the plant.

I've made several buck circuits without the need for any extra compensation, and they work very well. So i have to ask what kind of compensation are you using? I am thinking that a lot of op amps are already compensated for unity gain.

Typically a lead-lag network is used for compensation.

The circuit I am referring to is a standard buck regulator with linear negative feedback to regulate the output voltage. If you don't compensate for the LC resonant frequency, the regulator will oscillate. The only design I know of that doesn't require compensation is one with a hysteretic (bang-bang) loop.

The unity-gain compensation of an op amp doesn't compensate for the LC resonance. You can readily see that if you attach an LC circuit to the output of an op amp and take the negative feedback from the junction of the L and C.

What type of buck regulators did you make? What were the control circuits?

Don't know what a buck plant circuit is(?).

 

Hola Santa
Before you start getting busy in the North Pole, you could read AN 920 On Semi. Step down (buck) converters are explained. That could help you to round the basics. Even you could venture into step up ones. Pas difficile. Bonne chance!

 

Hola Santa
Before you start getting busy in the North Pole, you could read AN 920 On Semi. Step down (buck) converters are explained. That could help you to round the basics. Even you could venture into step up ones. Pas difficile. Bonne chance!

Hi,

I think it would be better if you stated exactly what you wanted to say
If you mean we should refresh by reading up on the subject, i think you are right. But there are also different aspect of the design which i think are coming into play here for this discussion. Stating "buck circuit" isnt good enough by itself, we have to specify a few more little details about what are intentions are. I'll get to this in the next post as i'd like to reply to Carl's post next.

 

Typically a lead-lag network is used for compensation.

The circuit I am referring to is a standard buck regulator with linear negative feedback to regulate the output voltage. If you don't compensate for the LC resonant frequency, the regulator will oscillate. The only design I know of that doesn't require compensation is one with a hysteretic (bang-bang) loop.

The unity-gain compensation of an op amp doesn't compensate for the LC resonance. You can readily see that if you attach an LC circuit to the output of an op amp and take the negative feedback from the junction of the L and C.

What type of buck regulators did you make? What were the control circuits?

Don't know what a buck plant circuit is(?).

Hi again,

In control theory the "plant" is considered the part of the circuit that has to be controlled, such as the RLC filter part which may include the load and may also include the PWM modulator. The PWM modulator is so well described that i feel that the RLC output filter is better off called the plant while the PWM modulator is just part of the driver. It does not include the feedback with or without any compensation.

Well, i did a complete analysis of the op amp (power op amp) and LC filter, and op amp and RLC filter, and i found that the complete response with just an LC filter was sinusoidal, which means it was actually an oscillator and had the form similar to:
Vout=A*cos(wt)+B*sin(wt)+C
(A, B and C constants where C might be zero)
so this is a pure sinusoidal output with no damping whatsoever. That means it puts out a sine wave, which of course we dont want

The analysis WITH series resistance for the inductor, a little series resistance for the capacitor, and a load resistance showed that an exponential factor comes into play:
Vout=e^(-a*t)*(A*cos(wt)+B*sin(wt))+C
(A, B, and C constants again but possibly different from before and C not equal to zero)
so this starts out as a sinusoidal response riding on a DC level, but then damps out to just a constant, C. That means it is stable as long as 'a' is large enough to not allow the sinusoidal part to dominate for too long. In practice, it seems that this is what happens. The output wiggles a little and then becomes a pure DC level, exactly what we'd want in a regulator, or at least almost.

So using an RLC plant the output always stabilizes and with typical values it stabilizes pretty fast, but with a pure LC plant it actually oscillates forever.

So what's with all the mention of compensation in the literature then? It is known that the buck circuit is a pretty stable circuit, it's the boost circuit that causes all the problems. But there's another aspect of the design which we had not looked at yet, and that is optimization.

Optimization means we want to get that exponential part to happen fast, so that our output gets up to the right voltage fast and stays there without too much bounce, and responds to line and load changes fast so we maintain regulation within reasonably short time periods. This is where the compensation really comes into play, because we can get the output to respond faster. That of course means the response starts to lean toward instability, so there's only so far we can go with that before the output will break up. This means the compensation has to be done right.

That's my conclusion here, that the compensation is really more about optimization rather than stability. The stability issue only comes into play when we try to get the most we can out of the circuit using added compensation, and when are successful with that then we get a faster circuit. There are many buck circuits which dont use any however, but now we know that they are sub optimal.
The drawback to the optimization idea however is the design will be more pinned to a given application where the load is known beforehand. If the load (or range of load change) is not known then it would be very hard to optimize (and compensate).

A better read i think might be the Texas Instruments paper slva301.pdf as they go into detail about the transfer function and stuff like that. It is pretty long though so i dont know if i care to read the whole thing right now as i have a bunch of stuff i have to do but if anyone is interested that would be a good thing to read i think.

I think an example of a buck circuit without compensation is the LM2576 Simple Switcher. I'd have to double check though to see what they are doing inside that chip. They have another one (cant remember the part, maybe LM2596 or something) that does require a compensation capacitor, but many designs dont use it and i'd have to double check to see why National Semi actually wanted to use that anyway (possibly for faster response).

 

I think it would be better if you stated exactly what you wanted to say

No more nor less than what I said, Señor Al.

If you mean we should refresh by reading up on the subject, i think you are right.

That "we" means you feel yourself alluded in some way. (?) My reply is / was addresed to the OP.

Myself, being one of the less qualified regulars in this and other 3 sites to suggest anything, I mentioned AN920 because, very few days ago, helped me to understand the most basic basics of step-down and setp-up converters. Vis a vis Father Christmas, I am just few days ahead of him in all this.

 

Responding to post 19:
That's exactly what I was thinking about. The key word is, "efficiently".
It is taught very early that a supply voltage chopped with a variable duty cycle square wave will deliver an output voltage something like Vsupply x duty cycle = Vout.
Yeah but...what if the load changes? One of my early, "can't figure out how this works" moments.

 

.....................................
I think an example of a buck circuit without compensation is the LM2576 Simple Switcher. I'd have to double check though to see what they are doing inside that chip. ...............................

If you look at the TI LM2576 data sheet it states in the first page under Description that "these regulators are simple to use and include internal frequency compensation".

 

If you look at the TI LM2576 data sheet it states in the first page under Description that "these regulators are simple to use and include internal frequency compensation".

Hello again,


Yes, but do they state *what* that compensation is for?
In my previous post i stated that there could be two reasons for including what we call "compensation".
Also in that post i pointed out that the equation for the basic buck circuit was stable when there was some resistance in the circuit without requiring any feedback compensation. That came from the circuit analysis of the buck circuit. I also pointed out that if we wanted faster response then we'd have to add what might be called "compensation" which really helps to optimize the circuit, which was already stable but too slow.
Compensation of the op amp internally also is not the same thing as loop compensation.
In the block diagram, they dont show any compensation except to mention that the op amp is of "Fixed Gain".
Also, if we do a sim of a power op amp with LC filter it will oscillate when there is no resistance in the circuit, but when we add a little series resistance to the inductor and a little load resistance, the damping comes into play and it becomes stable. I even found this to be true with relatively large load resistance. That's a linearized version of the buck like you were talking about.

Also, with the LM2596, you will find they use 'compensation' some times and dont use any other times.

What i would have to see is a simple buck circuit that oscillates without 'compensation' hopefully a linearized version. But it would have to have a reasonable sized output capacitor too though. I would not care about a design that used say 1uf output cap unless the switch frequency was very high.

BTW the linearized version uses a power op amp, voltage reference, inductor with small ESR, a filter capacitor with low ESR, and output load, possibly two resistors in the feedback path to divide the output down to the reference voltage so we can get higher outputs.

I am aware that you know what you are talking about, so i suspect that your reason for stating that compensation is required is for some practical reason that does not appear in the basic circuit theory because the basic circuit theory shows high stability. This practical reason should be identified however so we know what it is, but that would mean you would have to show a circuit that clearly shows everything inside that oscillates without the compensation and does not oscillate with it. Even then we would hope that we can figure out what it is that is not working as close to theory as we think, unless of course that also turns out to be optimization rather than compensation.
It is easy to confuse optimization with compensation, because optimization can look like compensation when we think of a 'slow' response as being an 'incorrect' response. In that case the 'compensation' makes the circuit work better, even though it's really 'optimization'.

LATER:
I am including three plots of a theoretical buck regulator. The circuit originally has just two resistors in the feedback path to set the output voltage at 5 volts with a 2.5v reference, so the two resistors are equal and are 1k each.
The 'top' resistor (one that connects to the output) is either alone or has a small value capacitor across it in the various plots.
The plot with C=0 has no parallel cap.
The plot with C=0.001uf has that value parallel cap.
The plot with C=0.01uf has that value in parallel.

So here we can see directly the effect of the 'compensation' capacitor.
With no cap (C=0) the response overshoots, but is still very stable.
With C=0.001uf we see the overshoot come down just a small amount.
With C=0.01uf we see the overshoot eliminated, but the response is a little slower.

So here we see the 'compensation' just made the buck circuit better, although it was always stable. The degree of stability might change however with increasing output voltage which means we'd see a couple more ripples before the response settled down. So we also see that some 'compensation' is nice to have in the circuit.

As a side note, it was fairly difficult to get the inverse Laplace Transform for the circuit with the compensation capacitor in it. Wolfram Alpha didnt know what the heck to do with the fairly complicated frequency domain transfer function and thought there might be a spelling error or something

 

Below is the simulation of a simple inverting LM324 op amp circuit with a 10k input and a 10k feedback resistor to the LC junction, and a series 100uH output inductor with a 100uF cap to ground, values as shown in the example for the LM2576. The transient output oscillated and the Bode plot showed a large 47dB peak at the LC resonant frequency. No reasonable amount of inductor resistance significantly affected that. So how would you eliminate that oscillation without feedback compensation?

 

The buck converter is actively switched at frequencies much higher than the LC resonant frequency.

 

The buck converter is actively switched at frequencies much higher than the LC resonant frequency.

Of course, but that normally doesn't have a significant effect on the control loop whose frequency response encompasses the LC resonant frequency. In modeling the control loop response, the switching frequency, if high enough, is often ignored and the PWM modulator modeled as a linear voltage gain block.

 

Below is the simulation of a simple inverting LM324 op amp circuit with a 10k input and a 10k feedback resistor to the LC junction, and a series 100uH output inductor with a 100uF cap to ground, values as shown in the example for the LM2576. The transient output oscillated and the Bode plot showed a large 47dB peak at the LC resonant frequency. No reasonable amount of inductor resistance significantly affected that. So how would you eliminate that oscillation without feedback compensation?

View attachment 76319

Hi again,

I am not entirely sure what i am looking at here. Is the output at "Out" the red plot?
What is that green plot, V(1) i think the label states.

Also, why drive the inverting input with a pulse?
Also, what are the pulse specifications?

If you could post the sim file i could take a better look. I might need the LM324 model too though im not sure i have that one. In the mean time i can try to set it up in another simulator.

I am not sure if a 'regular' op amp qualifies as a good driver for the plant, but ill consider it carefully anyway.

Oh yeah before i forget, add a little ESR between the output and the cap. Say 0.1 ohms to start, but go down as low as 0.01 ohms. See what effect that has on the output.

 

Of course, but that normally doesn't have a significant effect on the control loop whose frequency response encompasses the LC resonant frequency. In modeling the control loop response, the switching frequency, if high enough, is often ignored and the PWM modulator modeled as a linear voltage gain block.

If you want to exert control through PWM duty, I suppose your controlling algorithm will be good enough not to produce any oscillations (which may be hard to do if the nature of the load changes).

However, driving switching directly with comparator (Vout comared to the desired V), keep all the frequencies high and will not produce any oscillations. IMHO, this is a better (and simpler) way to control buck converter. This will produce overshoots, but they're inherent and cannot really be avoided. Imagine, the inductor blowing current into the output capacitor and the load suddently disconnects. Nothing you can do to prevent overshoot (unless you have some adittional circuicity to deal with it).

 

If you want to exert control through PWM duty, I suppose your controlling algorithm will be good enough not to produce any oscillations (which may be hard to do if the nature of the load changes).

However, driving switching directly with comparator (Vout comared to the desired V), keep all the frequencies high and will not produce any oscillations. IMHO, this is a better (and simpler) way to control buck converter. This will produce overshoots, but they're inherent and cannot really be avoided. Imagine, the inductor blowing current into the output capacitor and the load suddently disconnects. Nothing you can do to prevent overshoot (unless you have some adittional circuicity to deal with it).

Yes, the control is normally good enough to produce no oscillations or significant overshoot from no load to full load. The energy stored in a typical switching regulator inductor is typically not enough to generate a overshoot in the output voltage for typical values of output capacitance if the output load is suddenly removed. For example 1A flowing through a 100uH inductor will generate a peak overshoot of 100mV into a 470uF capacitor.

Driving a switching comparator directly from the output is commonly done and is called a hysteretic or bang-bang converter. It does not require any added compensation but does require a certain amount of output ripple voltage for its proper operation, so is only used in applications where such a ripple is not of concern to the load (or requires additional LC filtering on the output to reduce this ripple).

 

Hi again,

I was waiting for that extra info i asked for, but i probably dont need it anymore as i was able to reproduce the same basic waveforms shown in the picture with the ramp followed by small 'oscillation'. I used an LM358 which is basically the same as the LM324 except for the device count inside the package.

With the following values:
L=100uH
RL=1.0 Ohms (inductor ESR)
C=1000uf
RC=0 Ohms (cap ESR, increased later for comparison)
RLOAD=1000 Ohms

i see a tiny tiny 'ripple' like looking waveform riding on top of the normal DC output level (looking at the output voltage). Even with this tiny ripple however the circuit could still be deemed 'stable' because the dominate response takes it up to the DC level and then holds it there, even though there is a tiny variation (this is similar to the lower response plot seen in the picture posted previously). Having only 0.7v DC output though is probably too extreme because normally we'd have at least 3.3v output, which would probably reduce the variation percentage too.

But once the RC (resistance in series with the capacitor which is ESR) is introduced, all the tiny sinusoidally looking variations go away completely, just as predicted by the mathematics (with RL and RC that is). I tried values of 0.01 to 0.1 just to see what would happen, and even 0.01 got rid of the tiny 'ripple'. That's because the resistance introduces an exponential damping coefficient which decreases with time, and that coefficient is responsible for decreasing at least one of the sinusoidal terms in the final output. Without that, the sinusoidal part may never go away.

Unfortunately i did not include a zero ohms RC in the short mathematical 'study' i did i only included a zero ohms RC combined with a zero ohms RL to see that the output was then sinusoidal. To do that i would have to repeat the process which i might not be able to get to do today. But i suspect that when we reduce the ESR of the cap to zero we get some sinusoidal part of the response showing up at the output, but it is small and the dominate part of the response is the pure DC which is what we need. So with or without the cap ESR we still see what we can call a 'stable' operation, but with the small ESR of the cap even that goes away.

We also would have the internal part of the op amp to consider. The op amp is not ideal, and in pure theory it would be ideal. In the ideal setup i dont think we even need any cap ESR to get a smooth DC output but i wont press this until i get to try it using just regular circuit analysis by hand using just mathematics (no parasitics to bother the theories) and compare the output with and without the cap ESR and leaving a small inductor ESR.

I might edit this to add a few more things later if i can get time.

LATER:
Ok doing it mathematically there is a limit on R2 which will cause (or not) exponential damping. For the values given above, the turning point for the capacitor ESR comes out to equal 0.00874344498 Ohms. Anything under that will result in a small undamped sinusoidal part which shows up as looking like a small 'ripple'. Anything equal to or greater than that (like 0.01 Ohms) should result in a smooth output. That explains why when i used 0.01 the output smoothed out, and i did not go under that value except of course when i tried zero Ohms. But in any case it is quite small and the dominate response always seems to be stable. I'll have to try going lower than 0.01 (but not zero) in the simulation next and see how well the simulation matches up to theory, even given the sim op amp has it's own characteristics that the ideal op amp does not possess.

LATER LATER:
Ok, using an RC (cap ESR) value of 0.001 Ohms i see 20mv sinusoidal part riding on the 5vdc output, using 0.005 Ohms it goes down to less than 1mv, and of course with 0.009 Ohms it goes down to zero. I think using 0.005 Ohms also damps out to zero but it takes a lot longer than with 0.01 Ohms for example. This is again with the other values given above.

 

The energy stored in a typical switching regulator inductor is typically not enough to generate a overshoot in the output voltage for typical values of output capacitance if the output load is suddenly removed. For example 1A flowing through a 100uH inductor will generate a peak overshoot of 100mV into a 470uF capacitor.

This is a question of scale. Also depends on Vout. I came up with this approximate formula dV = L*I^2/(2*C*V). Your 100mV figure implies Vout of about 1V. At 12V, it'll be only 8mV. Almost nothing.

However, for 100A flowing through 2mH inductor in the same conditions, the formula produces dV = 1667V. That's different.

Of course, since dV is so big compare to Vout, the approximate formula doesn't work any more, and we need to use full formula dV = sqrt(I^2*L/C - V^2) - V. This one produces 188V, which is quite a bit of overshoot for 12V power supply.

Overshoots become real problem when you move to real power

 

Hi,

Yes, ha ha, i did one experiment with very very small ESR for the inductor and no ESR for the cap (not recommended) and the overshoot was 100 percent and lasted for 0.1 seconds! That's nasty

The inductor and capacitor ESR play a big part in these kinds of converters. In the boost circuit however the cap ESR is so important that the circuit will be completely unstable for some values of cap ESR that are too low. In that circuit it's not just a matter of a little 'ripple' on the output, it's the whole thing goes out of whack so there is no resemblance to a DC output left

These two resistances take the role of producing the size of the exponent in the exponential damping factors in the response. So the bigger the resistance, the faster the sinusoidal terms drop out. Tiny resistances mean it takes a long time to see the sine part go away.
For a reduced complexity example:
V(t)=e^(-a*t)*sin(w*t)

where 'a' reduced to only resistances becomes:
a=(((A+2)*R2+2*R1)*R3+2*R1*R2+2)/(4*R3+4*R2)

(A is the gain of the op amp, R1 is inductor ESR, R2 is cap ESR, R3 is the load resistance)

and from that we can see how the resistances affect the damping time (comparatively, not numerically).

 

Hi again,

The total solution with no inductor or capacitor ESR wasnt too difficult to get so i'll post it here if you'd like to compare your results:

Vout(t)=ax*((-sin(wo*t)/(2*wo*C1*R3)-cos(wo*t))*e^(-t/(2*C1*R3))+1)

where
R3 is the load resistance,
ax=(A*E1)/(A*B+1)
wo=sqrt(L1*((4*A*B+4)*C1*R3^2-L1))/(2*C1*L1*R3)
A is the gain of the op amp,
B is the feedback voltage divider ratio always 1 or less, so two 10k resistors would make B=0.5 because 10/20=0.5 and those two resistors are assumed to be much higher than the load resistance.
C1 and L1 are the plant inductor and capacitor, we've used 1000uf and 100uH before.
E1 is the reference voltage, typically 2.5v so with E1=2.5 and B=0.5 the output DC will be very close to 5 volts (see 'ax' above which is also the DC output level).

The equation is valid when:
(4*A*B*C1*R3^2+4*C1*R3^2-L1)>0
which is the most typical case, and that's the case when we have some sinusoidal part in the response (obvious from Vout above).

Some more simplification of the output equation is probably possible.

 

Hi,

What i find is that the inductor cap combination frequency is almost always much lower than the switching frequency, so it is treated almost like it was not there at all. For example, a 1kHz resonant frequency vs 50kHz switching frequency, the control circuit sees only a very slow variation due to the LC combination, which makes it look almost like a simple slowly varying load change...which it is able to handle no problem.
It's only when the switching frequency is too close to the LC frequency that trouble might begin because then the control circuit might see an increase in output with a decrease in control signal, which means it's out of control.
There's also the damping to consider, if the inductor has higher resistance it wont oscillate even under some bad conditions.

Very insightful. Thanks