The exact information on SPI communication is not explicitly stated so I'm guess there's a little bit "reading between the lines" should be employed.
According to my ability to read timing diagrams and reading between the lines...

MISO(sdo) is mode 1 and MOSI (sdi) is mode 0
And WR/FSYNC plays the role of Slave Select. Where does the clock phase and polarity come into play

Except from ad2s1210 datasheet
SERIAL INTERFACE
The serial interface is selected by holding the SOE pin low. The AD2S1210 serial interface consists of four signals: SDO, SDI,
WR/FSYNC, and SCLK. The SDI is used for transferring data into the on-chip registers whereas the SDO is used for accessing
data from the on-chip registers, including the position, velocity, and fault registers. SCLK is the serial clock input for the device, and all data transfers (either on SDI or SDO) take place with respect to this SCLK signal. WR/FSYNC is used to frame the data. The falling edge of WR/FSYNC takes the SDI and SDO lines out of a high impedance state. A rising edge on WR/FSYNC returns the SDI and SDO to a high impedance state. The CS input is not required for the serial interface and should be held low. SDO Output In normal mode of operation, data is shifted out of the device as a 24-bit word under the control of the serial clock input, SCLK. The data is shifted out on the rising edge of SCLK. The timing diagram for this operation is shown in Figure 32. SDI Input The SDI input is used to address the on-chip registers and as a daisy-chain input in configuration mode. The data is shifted into the part on the falling edge of SCLK. The timing diagram for this operation is shown in Figure 32

 

https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Clock_polarity_and_phase

I think you're right that the mode is 1,0 that is
CPOL = 1, clock normally high, data valid on the high-low transition.
CPHA = 0, data is sampled on the high-low transition of the clock.
Data shifts on the low-high transition of the clock.

I usually just think of it in terms of what clock edge the data gets sampled on and so it shifts on the other edge. Then I look at the quiescent clock level. But it looks like SPI would call it mode 1,0 so there' you go.

WR-/FSYNC- on this chip is a combination of SPI slave select SS/ and data latch control. Unlike a lot of SPI, this one does only one byte per WR-/FSYNC- cycle. Drop the line, do the 8 bit SPI then raise the line to latch that data. Drop it again to send the next 8 bits then raise it to latch the byte and so on.

The SPI slave's outputs are HIz when WR-/FSYNC- is high so you can have more than one device on the bus.

I think you're on the right track, SPI-wise. What are you using to drive it?
Good luck!

 

https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Clock_polarity_and_phase

I think you're right that the mode is 1,0 that is
CPOL = 1, clock normally high, data valid on the high-low transition.
CPHA = 0, data is sampled on the high-low transition of the clock.
Data shifts on the low-high transition of the clock.

I usually just think of it in terms of what clock edge the data gets sampled on and so it shifts on the other edge. Then I look at the quiescent clock level. But it looks like SPI would call it mode 1,0 so there' you go.

WR-/FSYNC- on this chip is a combination of SPI slave select SS/ and data latch control. Unlike a lot of SPI, this one does only one byte per WR-/FSYNC- cycle. Drop the line, do the 8 bit SPI then raise the line to latch that data. Drop it again to send the next 8 bits then raise it to latch the byte and so on.

The SPI slave's outputs are HIz when WR-/FSYNC- is high so you can have more than one device on the bus.

I think you're on the right track, SPI-wise. What are you using to drive it?
Good luck!

Initially just an Arduino to make to it even works

 

Your concern is the clock signal, SCLK.

You can have SCLK normal or inverted.
Then you choose which edge of the clock is responsible for clocking the shift registers, the leading or trailing edge of the clock.

Now you have four possible combinations, or four modes.
Choose one and make sure both master and slave are set to the same mode.

 

Your concern is the clock signal, SCLK.

You can have SCLK normal or inverted.
Then you choose which edge of the clock is responsible for clocking the shift registers, the leading or trailing edge of the clock.

Now you have four possible combinations, or four modes.
Choose one and make sure both master and slave are set to the same mode.

I
guess I thought the Mode was hardware locked as I dont see anything that allows for SPI perameter configurability relative to the ad2s1210

 

I
guess I thought the Mode was hardware locked as I dont see anything that allows for SPI perameter configurability relative to the ad2s1210

The AD2S1210 SPI is fixed. The Arduino SPI just needs to be configured to match.

 

The AD2S1210 SPI is fixed. The Arduino SPI just needs to be configured to match.

I guess what is confusing the heck out of me is

SDO data be shifted out on the rising edge of SCLK.

SDI data be shifted out on the falling edge of SCLK.

And how does this relate to MODE?

SDO Output
In normal mode of operation, data is shifted out of the device as a 24-bit word under the control of the serial clock input, SCLK. The data is shifted out on the rising edge of SCLK. The timing
diagram for this operation is shown in Figure 32.
SDI Input
The SDI input is used to address the on-chip registers and as a
daisy-chain input in configuration mode. The data is shifted into the part on the falling edge of SCLK.

 

If you look at the figure in #1, both SDO (MISO) and SDI(MOSI) are sampled on the falling edge of SCLK and shifted on the rising edge. The delays shown like t24 are exaggerated for easier viewing. The clock is quiescently high. By definition, that is SPI mode 1,0.

Note that 'MODE' is just a shorthand label to describe the SPI bus setup. As I indicated earlier, I am less comfortable with using 'mode' and just look at what I need for the slave then look at the datasheet of the master to see how I have to configure the SPI module to do that. If it winds up as MODE 1,0 so be it.

I don't use Arduino but @djsfantasi does and probably knows the particulars / setup parameters for this.

 

If you look at the figure in #1, both SDO (MISO) and SDI(MOSI) are sampled on the falling edge of SCLK and shifted on the rising edge. The delays shown like t24 are exaggerated for easier viewing. The clock is quiescently high. By definition, that is SPI mode 1,0.

Note that 'MODE' is just a shorthand label to describe the SPI bus setup. As I indicated earlier, I am less comfortable with using 'mode' and just look at what I need for the slave then look at the datasheet of the master to see how I have to configure the SPI module to do that. If it winds up as MODE 1,0 so be it.

I don't use Arduino but @djsfantasi does and probably knows the particulars / setup parameters for this.

Ok, lots to unpack there, guess I better do my due diligence and study up timing diagrams because you're seeing things that I have no idea how you are seeing what you are seeing . Maybe as a hint, can you tell me how you are seeing the SCLK is "quiescently high"?

 

Look at the logic level before the data transfer sequence begins.

 

Ok, I seen that earlier but thought way to easy

 

Ok, I seen that earlier but thought way to easy

That's the thing, the SPI shift register interface is easy because it was designed by hardware engineers instead of programmers. It's the programming protocol of data exchanges and timing that might be hard.