The project I was working on at that time (1995) was the first 0.25u design at my company.

Then I probably got the number wrong. I suppose that .35 μm might have been closer to the mark.
I vividly remember the palpable sense of tension for almost a year about avoiding the necessity of having to pay a second masking charge (I forget the magnitude) if the first silicon did not perform. There is nothing like it to focus the mind and encourage teamwork.

 

Then I probably got the number wrong. I suppose that .35 μm might have been closer to the mark.

There were companies doing designs with the old processes. The 4" factories needed to be kept full so they didn't become a drain on profits. The company I worked for tried to stay on the bleeding edge because smaller process nodes gave about a 50% shrink in die area.

 

There were companies doing designs with the old processes. The 4" factories needed to be kept full so they didn't become a drain on profits. The company I worked for tried to stay on the bleeding edge because smaller process nodes gave about a 50% shrink in die area.

Did you ever measure die area in picoacres?

 

Did you ever measure die area in picoacres?

No. Die size was still measured in mils, so we used square mils.

Wafer diameters were also in inches. 0.25u was started on 6", then migrated to 8".

 

I'll order the first sleeve of 10 when the chip is launched - If it comes with a reasonable IDE, automotive qualifications for under the hood applications, commitment to continue production for at least 8 years, and the OPs company willing to post a $250M bond or equivalent to cover recalls related to the chip.

 

About 20 years ago my small group designed an ASIC. The engineer who did so had never done anything like that before (but he is a really sharp engineer). Going through our ASIC vendor, we hired a specialist to design a PLL that we needed in the design. The ASIC vendor also suggested the software tools my engineer would need to design and test the ASIC design. As I recall, all of the software ran on a 100 MHz X86 machine and did not break the bank. Not only that, but the ASIC worked and made it into production.

It might pay to take your questions to your silicon foundry partner and ask them what tools they prefer you to use.

 

I will say that floor planning just might be a place where you can help the foundry. I would not imagine they would have a problem with your input at that level.

 

I worked on a chip at Intel. I was on the software side, C compiler specifically, not hardware, But I was in the same group with the hardware designers.

They used a tool developed internally to design at the gate level. It had a graphic interface and simulation, very much like LTSPICE, with a nice library of gates, flip-flops, registers, multiplexers, adders, memory cells etc.

I learned the tool by developing a simple pipe-lined processor, way beyond anything I had done before.

But the actual design of the logic gates, at the transistor level was done by manufacturing, not the design team, they did not go to that level.

And the layout on the silicon was done almost entirely by another piece of software, with human intervention required when it coukd not route or meet timing criteria.

I doubt that you really want to go to the level of layout.

Bob

 

I worked on a chip at Intel. I was on the software side, C compiler specifically, not hardware, But I was in the same group with the hardware designers.

They used a tool developed internally to design at the gate level. It had a graphic interface and simulation, very much like LTSPICE, with a nice library of gates, flip-flops, registers, multiplexers, adders, memory cells etc.

I learned the tool by developing a simple pipe-lined processor, way beyond anything I had done before.

But the actual design of the logic gates, at the transistor level was done by manufacturing, not the design team, they did not go to that level.

And the layout on the silicon was done almost entirely by another piece of software, with human intervention required when it coukd not route or meet timing criteria.

I doubt that you really want to go to the level of layout.

Bob

It's really cool what you can learn on the way to doing other things.

 

And the layout on the silicon was done almost entirely by another piece of software, with human intervention required when it coukd not route or meet timing criteria.

Might that have been the Intel developed cell place and route tool called DAPR (that used Timberwolf as it's placement engine)?

 

https://www.synopsys.com/

Also note typical expected costs for a new chip:

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You could probably get started if you have say 100 million available.

https://semiengineering.com/how-much-will-that-chip-cost/#:~:text=While projections show it will,is plenty of reusable IP.

could you please explain where would these 100 million go?
Lets say, an engineer from India or Russia or China is paid 2,000USD per month (good salary for their 3rd world country) . At 2k salary per month you would hire 4,166 people for an entire year. What is that part that is so complicated that you need 4 thousand people working for an entire year to finish the design of a chip, I just don't get it. Where is the money going? There must be some "budget black hole" there. There is a "Software" item on your chart wich is ranging probably in 200 million range, for 200 million you can hire lots of developers who can build an entire operating system like Linux for you. What kind of software is that , that you need to spend 200 million on it?

 

could you please explain where would these 100 million go?
Lets say, an engineer from India or Russia or China is paid 2,000USD per month (good salary for their 3rd world country) . At 2k salary per month you would hire 4,166 people for an entire year. What is that part that is so complicated that you need 4 thousand people working for an entire year to finish the design of a chip, I just don't get it. Where is the money going? There must be some "budget black hole" there. There is a "Software" item on your chart wich is ranging probably in 200 million range, for 200 million you can hire lots of developers who can build an entire operating system like Linux for you. What kind of software is that , that you need to spend 200 million on it?

Then you should do that. If you see an opportunity to supply a product or service at better VALUE, the market will reward you with their business. It's called capitalism. It takes work, financial risk, time, ability to establish trust, innovation to build your own portfolio of intellectual property or license patents from existing players, and trust from investors to support your effort. You have a lot of work ahead of you. ..And I'm not sure you are building trust with your potential customers or investors by asking basic questions on an electronics forum.

 

could you please explain where would these 100 million go?
Lets say, an engineer from India or Russia or China is paid 2,000USD per month (good salary for their 3rd world country) . At 2k salary per month you would hire 4,166 people for an entire year. What is that part that is so complicated that you need 4 thousand people working for an entire year to finish the design of a chip, I just don't get it. Where is the money going? There must be some "budget black hole" there. There is a "Software" item on your chart wich is ranging probably in 200 million range, for 200 million you can hire lots of developers who can build an entire operating system like Linux for you. What kind of software is that , that you need to spend 200 million on it?

I can't answer those questions myself but I doubt there is any "black hole". Since the earliest days integrated circuits have been expensive and could only be affordable by selling very large volumes, that's how the large up-front investment would be recouped.

You could do some research to get a better understanding of the costs, this can only be helpful to you, to understand more about an industry that you intend to enter and compete in, why not get a job in one of these firms for a few years, the stuff you'd learn would be hugely valuable.

Simply calculating how many person hours you could get with 200 million USD is naïve, there are all kinds of costs besides salaries.

Maybe you can get this down to 30 Million, this article explains how, here's some snippets:

Getting back to the math for a design team of 100 people. Salaries for chip developers have closed the gap (downward) with other engineers, but the whole talent pool has seen a massive increase in compensation in recent years. So let’s say that a fully-loaded designer costs an average of $300,000 per year (25,000 per month), or $30 million in headcount for 100 people.

 

I can't answer those questions myself but I doubt there is any "black hole". Since the earliest days integrated circuits have been expensive and could only be affordable by selling very large volumes, that's how the large up-front investment would be recouped.

You could do some research to get a better understanding of the costs, this can only be helpful to you, to understand more about an industry that you intend to enter and compete in, why not get a job in one of these firms for a few years, the stuff you'd learn would be hugely valuable.

Simply calculating how many person hours you could get with 200 million USD is naïve, there are all kinds of costs besides salaries.

Maybe you can get this down to 30 Million, this article explains how, here's some snippets:

This doesn't account for benefits and overhead. It is well know that engineers can hardly be expected to manage themselves, or work without access to support staff. It also does not count for the capital investment in a fab for a new process or the rental of an existing fab for some portion of its productivity.

 

What is that part that is so complicated that you need 4 thousand people working for an entire year to finish the design of a chip, I just don't get it.

You don't need 4 thousand people.

You need to specify your timeframe (3 months, 6 months, 2 years), what collateral is available to you, what do you need to design. How many people do you plan to hire? What is their experience level?

As I understand it, the architecture is open source. Does the collaboration provide hard IP? If so, how much glue logic do you require?

If you're starting layout from scratch, you need to define your layout strategy. Are you going to use standard blocks (cells), are you going to be full custom? Are you going to route manually or with software?

You're going to need design engineers, layout designers, and support people in a number of disciplines. The foundry will tell you which tools are compatible with their rule decks for design rule checking and connectivity verification. I don't know what foundries offer in the way of performance or reliability verification.

 

I have $68 ready for my sleeve of 10, ready to buy something better than I get now.