# What software do IC foundries use to lay out IC components?

#### nulik

Joined Mar 4, 2021
4
What software can I use to design an integrated circuit ? I need the same software that chipmakers use. I am working on a startup to create a 64bit RISC V processor with embedded FPGA fabric. So, for 22, 32 and 40nm , what software can I use to prepare all the layers so I can later send the design to TSMC or GlobalFoundries and this way it would go directly to manufacturing without hiring expensive engineers at TSMC. I want to save on NRE. Is there any open source tool I can use? I have read it costs from a few million to 500 million to make a chip, there is no way I will ever have that amount of money.

#### MrChips

Joined Oct 2, 2009
26,774
What software can I use to design an integrated circuit ? I am working on a startup to create a 64bit RISC V processor with embedded FPGA fabric. So, for 22, 32 and 40nm , what software can I use to prepare all the layers so I can later send the design to TSMC or GlobalFoundries and this way it would go directly to manufacturing without hiring expensive engineers at TSMC. I want to save on NRE. Is there any open source tool I can use? I have read it costs from a few million to 500 million to make a chip, there is no way I will ever have that amount of money.
Seems like a rather strange question.
If you are creating a 64-bit RISC processor one would assume that you would already have the resources to answer these questions.

#### BobTPH

Joined Jun 5, 2013
5,451
Mylar sheets and stick on decals. Hey, it worked for PCB design 50 years ago. I know, because I designed one that way.

Bob

#### dl324

Joined Mar 30, 2015
14,897
Is there any open source tool I can use?
I can't think of any entity seriously considering such a project to not be willing to pay for commercial tools. I know of companies that designed their own tools, but it wasn't inexpensive to go that route.

You should contact prospective foundries and find out what software their design collateral is compatible with.

#### Papabravo

Joined Feb 24, 2006
18,964
Nobody I know could possibly do their own chip layout. Only the foundries do it, because they know their processes and THEY ARE PROPRIETARY. You use a variety of design tools including schematic capture, VHDL, Verilog, or other hardware description tools. You get your sims, or an FPGA prototype working and they do the rest. It has been like this for almost 30 years, since at least the days of 2 μm. feature size (ca. 1994). We are now approaching 3 orders of magnitude smaller feature size. I doubt seriously that you could obtain such tools unless you had the capital to acquire the foundry. I don't think TSMC is on the market at the moment.

#### crutschow

Joined Mar 14, 2008
30,419
So do you or someone you know have the expertise to design and lay out a 64-bit processor?
Software is not the problem (although good layout software will likely cost a few $100k) but the design expertise and effort to make the chip is. The nature of your question implies that you don't really know what is involved in such a task. There's a good reason that the design of such chips typically cost$millions to make and that only large companies like Apple, AMD, and Intel can afford to do it.

The only way I see this working is if you have a good enough idea for this chip that you can get investment funding to build the chip.

#### nulik

Joined Mar 4, 2021
4
Nobody I know could possibly do their own chip layout. Only the foundries do it, because they know their processes and THEY ARE PROPRIETARY. You use a variety of design tools including schematic capture, VHDL, Verilog, or other hardware description tools. You get your sims, or an FPGA prototype working and they do the rest. It has been like this for almost 30 years, since at least the days of 2 μm. feature size (ca. 1994). We are now approaching 3 orders of magnitude smaller feature size. I doubt seriously that you could obtain such tools unless you had the capital to acquire the foundry. I don't think TSMC is on the market at the moment.
but they will still have to convert my gate logic to mask layers and what I want to do is to reduce costs to the minimum by advancing the design on my side. I am pretty sure that if I hire engineers outside instead of hiring engineers of the foundry it is going to be much cheaper at the end. The prices for chip making are absolutely insane. Hence my reason to ask for the software. For example, I have found that Magic software (which is actually open source) is very suitable for lying out layers and making the step further in the design. This design then can be exported to CIF or GDS file and this the foundry can reuse it to adapt to their own process. But I still have not cleared the question: what is the best software I have to use to maximally cut design costs? Magic can work, but is it the best tool to use?

#### nulik

Joined Mar 4, 2021
4
So do you or someone you know have the expertise to design and lay out a 64-bit processor?
Software is not the problem (although good layout software will likely cost a few $100k) but the design expertise and effort to make the chip is. The nature of your question implies that you don't really know what is involved in such a task. There's a good reason that the design of such chips typically cost$millions to make and that only large companies like Apple, AMD, and Intel can afford to do it.

The only way I see this working is if you have a good enough idea for this chip that you can get investment funding to build the chip.
The reason chips cost millions is the result of the monopoly of AMSL. This is the only company in the world that makes lithography machines that are used in chipmaking process. One machine costs 120 million dollars , AMSL has 2 years of backorders and its only market is sized at 150 billion dollars, almost at the same level as Tesla has. They even dear to ban sales to China because the US government asked us to help them in US-China trade wars. In the mean time, we have to pay 250 bucks per every manufactured chip. Read the full story here: https://www.brookings.edu/techstrea...e-at-the-center-of-chinese-dual-use-concerns/

I am pretty much aware of what is involved in such task and it is not very complex stuff. the RISC sources have been published so I can download it from open cores and adapt. The SRAM is just bunch of transistors. The FPGA is just bunch of LUTs wired together. As for timing analysis I am not worried because I am not going to have paths larger than 20. I am not going to design a GPU-kind of processor or the latest AMD Ryzen Zen3 chip. It is going to be simple chip for specific application of machine learning. This work has been done before and the difficulty is low. Right now i am on the business plan stage and I need to know what is the bugdget need have in order to run this project. That's why I asked about the software so I can download it study it and figure out if there is a way to cut design costs.

#### Papabravo

Joined Feb 24, 2006
18,964
but they will still have to convert my gate logic to mask layers and what I want to do is to reduce costs to the minimum by advancing the design on my side. ...
That is exactly the step that customers seldom if ever do. If you want to break the mold, by all means be my guest. You're going to have to try to do it one software package at a time. That means trying them one by one, because I have not seen too many reviews by users out there. As you point out the cost of building a foundry is even more astronomical than building a chip. Figure out who your foundry is going to be and work with them. You really have no other choice. That's the way the Mecedes Benz.

#### crutschow

Joined Mar 14, 2008
30,419
I am pretty much aware of what is involved in such task
Okay.
In order to do the layout, you will need the design rules from the foundry, (and each foundry is likely different) so you need to contact some foundries and see if they will work with you, and what they recommend for design tools.
If you don't need state-of-the-are process feature size and can use an older process, that will likely reduce the design difficulty and cost.

Design software from Cadence (apparently the most used), Mentor, and Tanner appear to be among the top tools.

#### Papabravo

Joined Feb 24, 2006
18,964
The importance of @crutschow 's point: " In order to do the layout, you will need the design rules from the foundry, (and each foundry is likely different) " cannot be overstated. It says that there is literally nothing you can do because they are unlikely to tell you what their design rules are. For leading edge processes they are proprietary and for older process they don't have the time, or the staff, or the patience to educate you. It is just all around easier for them to take your input and just do it.

#### dl324

Joined Mar 30, 2015
14,897
The reason chips cost millions is the result of the monopoly of AMSL. This is the only company in the world that makes lithography machines that are used in chipmaking process.
The vendors of other litho equipment will be shocked to hear this. If ASML was the only game in town, the high end semiconductor business would be in trouble because EUV was very very late and throughput is still very small compared to what semi manufacturers want.

While waiting for ASML to deliver EUV machines, they resorted to using 2-4 masks per layer using 193nm immersion lithography (at least down to the 10nm node; the last I worked on).

The SRAM is just bunch of transistors.
SRAM is the highest density area in a microprocessor and it isn't just a bunch of transistors. The SRAM will use the tightest rules to get the most density while having high yield. At the company I worked at, SRAM layout had to be checked by the process group to make sure it would be high yielding.

I'm pretty sure they still incorporate spare rows and columns of SRAM so they can repair otherwise good die. I know the company I worked for was doing it on 22nm because they talked about yield after repairing.

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#### crutschow

Joined Mar 14, 2008
30,419
they are unlikely to tell you what their design rules are.
The process is proprietary, but I would think they would give out the layout rules, especially for older processes.
That requires little education from the vendor.

#### Papabravo

Joined Feb 24, 2006
18,964
The process is proprietary, but I would think they would give out the layout rules, especially for older processes.
That requires little education from the vendor.
Admittedly my experience with foundries may be out of date. We were kept pretty much in the dark about the details. They did look at our design and make "suggestions", but we never received so mach as a scrap of information about the layout process.

#### dl324

Joined Mar 30, 2015
14,897
Having a design rule document and knowing how to use the rules effectively are two different things. When I worked on microprocessor design, I was responsible for layout verification. Part of my time was spent providing training sessions to all of the layout designers explaining some of the more complicated rules.

There were numerous times when I had to ask the process group for clarification of rule intent that wasn't included in the rule book.

In addition to complying with design rule requirements, we had additional requirements for making the layout more robust (extending endcaps, having redundant contacts/vias, loosening up layout where possible, laying out devices so they were less susceptible to process variation).

Performance and reliablility verification were separate disciplines.

No one in their right mind would skimp on any phase of design verification. The penalty for not doing it right the first time was high (billions of dollars).

#### Papabravo

Joined Feb 24, 2006
18,964
Having a design rule document and knowing how to use the rules effectively are two different things. When I worked on microprocessor design, I was responsible for layout verification. Part of my time was spent providing training sessions to all of the layout designers explaining some of the more complicated rules.

There were numerous times when I had to ask the process group for clarification of rule intent that wasn't included in the rule book.

In addition to complying with design rule requirements, we had additional requirements for making the layout more robust (extending endcaps, having redundant contacts/vias, loosening up layout where possible, laying out devices so they were less susceptible to process variation).

Performance and reliablility verification were separate disciplines.

No one in their right mind would skimp on any phase of design verification. The penalty for not doing it right the first time was high (billions of dollars).
Just to be clear, my experience was in the 1993-1994 time frame the CMOS process was 2μm. The ASIC was a network communications ASIC. My contribution to the design was to constuct multiple prototypes out of PALs and Xilinx FPGAs that ran at 1/10 th of the network speed to test firmware and other concepts. I was in all the meetings between the design team and the foundry people and they were inscrutable when it came to process details. Fortunately the first silicon actually did fly right, and I got an attaboy for building enough network boards so they could run experiments on an actual network and gather data. As a side project I had to construct the clock recovery circuit for the receiver out of F series and fast PALs to run at full speed. That worked as well.

#### dl324

Joined Mar 30, 2015
14,897
Just to be clear, my experience was in the 1993-1994 time frame the CMOS process was 2μm.
State of the art in that time frame was 0.35u. Bleeding edge was 0.25u.

#### Papabravo

Joined Feb 24, 2006
18,964
State of the art in that time frame was 0.35u. Bleeding edge was 0.25u.
It's possible I got the number wrong, and I'm not sure if it was bleeding edge (I don't think so) or not. It has been a while. I also remember the enormous and heavy monitors that came with the Mentor Graphics workstations that were 68000 based. Regular employees were NOT allowed to move them due to the risk of back injury. It took a two person team.

#### ApacheKid

Joined Jan 12, 2015
724
What software can I use to design an integrated circuit ? I need the same software that chipmakers use. I am working on a startup to create a 64bit RISC V processor with embedded FPGA fabric. So, for 22, 32 and 40nm , what software can I use to prepare all the layers so I can later send the design to TSMC or GlobalFoundries and this way it would go directly to manufacturing without hiring expensive engineers at TSMC. I want to save on NRE. Is there any open source tool I can use? I have read it costs from a few million to 500 million to make a chip, there is no way I will ever have that amount of money.
https://www.synopsys.com/

Also note typical expected costs for a new chip:

You could probably get started if you have say 100 million available.

https://semiengineering.com/how-muc...ections show it will,is plenty of reusable IP.

#### dl324

Joined Mar 30, 2015
14,897
It's possible I got the number wrong, and I'm not sure if it was bleeding edge (I don't think so) or not.
The project I was working on at that time (1995) was the first 0.25u design at my company.