For example in DACs, what exactly update rate?

 

My clock indicates seconds, but I only check the time occasionally.

 

My clock indicates seconds, but I only check the time occasionally.

But that could be the same thing as sampling

 

Sampling is an "input" type activity. Updating a DAC is an "output" type activity. Unlike sampling the are no real requirements imposed on updating. You can do it as fast or as slow as the application allows.

 

Sampling is an "input" type activity. Updating a DAC is an "output" type activity. Unlike sampling the are no real requirements imposed on updating. You can do it as fast or as slow as the application allows.

If the DAC has some stray capacitances that creates some settling time to achieve its final value, having a lower update ratemeans that error at the output will be lower? I say that because the output will be sampled later in the time so the output voltage may have well passed its settling time

 

Who says a DAC output has to settle? You might not be happy with the results, but there is no theoretical reason why you cannot update either faster or slower, as the mood move you.

 

Sample rate is how often an ADC takes samples. Update rate is how often a DAC produces new output voltages.
One thing that comes to my mind which might confuse the terms is how many samples of the signal you need to take with and ADC before the output digital data matches that first sample. Or in other words, some delta/sigma ADCs have a digital filter pipeline inside, so when you measure a sample now in step 1 you need to do another 2-3 measurement cycles before the data value of the first sample appears accurately in the output data register.
Say your ADC can do 1000 samples per second. But if you multiplex different inputs to one ADC, then after you switch on the desired input channel you take the sample, but have then have to take 2-3 "dummy" sample cycles for the result to go thorugh the pipeline, only after that you can switch to the next channel.
And a similar processing delay is likely also present in delta/sigma DACs, but I never designed anything with those.