hello
I'm trying to learn more about synchronous circuits, and to solve some questions.
here, how do i deal with those "delays" (in red) ? what happens when I send that kind of signal to a FF?
I'll be glad for some explanation about that.
thanks

 

hi lidor,
As this Homework, show what you think the LOW going change on the Data Input will appear on the FF output.??

The IN data State , clocked into the FF on the next rising edge of the Clock signal.

Is that what you mean.?
E
https://www.google.com/search?sxsrf=AOaemvJGZrqwLGcdWlg5QN_yIPmHDEMztg:1633677186871&source=univ&tbm=isch&q=synchronous+flip+flop+waveform&client=firefox-b-d&fir=aZeNdEwPo1EKvM%2C93LXtEHqHmV-SM%2C_%3B_QZRq1gFrh9btM%2CASaAmMkue-0yfM%2C_%3BJ7w__yZZagBVGM%2C93LXtEHqHmV-SM%2C_%3B5IPNr2-XSz0MhM%2C9_hgbisC_e5AeM%2C_%3BumILBm9ie2mkbM%2Co2J-9jW5RgSvKM%2C_%3BgrOh4VP6nhrvsM%2Cjnxp3ISbQ0YhfM%2C_%3BXFaPtAEUX2WMkM%2CCHcTtZwi07pVWM%2C_%3B1moihryjXGwVIM%2Co2J-9jW5RgSvKM%2C_%3BK6hANFbTNXoJNM%2CzGSO47WgmpdssM%2C_%3BSQlJxfaO3kspCM%2C93LXtEHqHmV-SM%2C_&usg=AI4_-kSCNeuYHuVvGszRZWCRHmZbr4OZoQ&sa=X&ved=2ahUKEwj-o5rjobrzAhXS3KQKHRaBAo0QjJkEegQICBAC&biw=1463&bih=856&dpr=1

 

hello
I'm trying to learn more about synchronous circuits, and to solve some questions.
here, how do i deal with those "delays" (in red) ? what happens when I send that kind of signal to a FF?View attachment 249810
I'll be glad for some explanation about that.
thanks

The whole point of a synchronous circuit is that everything happens on the clock edge. In your case, the rising edge of the clock. The circuit ignores anything that happens between clock edges. It synchronises everything to the clock.

 

hello
I'm trying to learn more about synchronous circuits, and to solve some questions.
here, how do i deal with those "delays" (in red) ? what happens when I send that kind of signal to a FF?View attachment 249810
I'll be glad for some explanation about that.
thanks

Hi,

What kind of FF are you dealing with here.
There are different types like D type, T, JK, JK master/slave.
For example, if this was a D type (with D the input) the output shown in your first post would not be correct.

 

You timing diagram should also be cognizant of setup and hold times. Violations of these requirements can result in metastability, where a Flip-flop may take an indeterminate amount of time to decide on it's output state.

 

how do i deal with those "delays" (in red) ? what happens when I send that kind of signal to a FF?

Why do you think you have to deal with them? What type of flip flop are you using?

 

@lidor250 You need to show us a schematic of your circuit that produced the timing diagram in post #1. That timing diagram is not consistent with a solitary flip-flop. It is possible that the output comes from a state machine consisting of 2 or more flip-flops.