Wave Diagram

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lidor250

Joined Oct 2, 2021
6
hello :)
I'm trying to learn more about synchronous circuits, and to solve some questions.
here, how do i deal with those "delays" (in red) ? what happens when I send that kind of signal to a FF?1.png
I'll be glad for some explanation about that.
thanks :)
 

Ian0

Joined Aug 7, 2020
3,754
hello :)
I'm trying to learn more about synchronous circuits, and to solve some questions.
here, how do i deal with those "delays" (in red) ? what happens when I send that kind of signal to a FF?View attachment 249810
I'll be glad for some explanation about that.
thanks :)
The whole point of a synchronous circuit is that everything happens on the clock edge. In your case, the rising edge of the clock. The circuit ignores anything that happens between clock edges. It synchronises everything to the clock.
 

MrAl

Joined Jun 17, 2014
8,548
hello :)
I'm trying to learn more about synchronous circuits, and to solve some questions.
here, how do i deal with those "delays" (in red) ? what happens when I send that kind of signal to a FF?View attachment 249810
I'll be glad for some explanation about that.
thanks :)
Hi,

What kind of FF are you dealing with here.
There are different types like D type, T, JK, JK master/slave.
For example, if this was a D type (with D the input) the output shown in your first post would not be correct.
 

Papabravo

Joined Feb 24, 2006
17,240
You timing diagram should also be cognizant of setup and hold times. Violations of these requirements can result in metastability, where a Flip-flop may take an indeterminate amount of time to decide on it's output state.
 

Papabravo

Joined Feb 24, 2006
17,240
@lidor250 You need to show us a schematic of your circuit that produced the timing diagram in post #1. That timing diagram is not consistent with a solitary flip-flop. It is possible that the output comes from a state machine consisting of 2 or more flip-flops.
 
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