Voltage Spikes in ADC

Discussion in 'Homework Help' started by Luce Sky Walker, Feb 17, 2017.

  1. Luce Sky Walker

    Thread Starter New Member

    Feb 17, 2017
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    Hey guys, in my last lab work i found a question that none of my classmates could help me with, and im not sure about the answer either. The circuit in question is an ADC with a transmission gate as a analog switch. The question of justifying the transitory of a signal when the clock changes state. V(2) is the tension after the 50ohm resistor. When the clock signal goes down happens the same thing but with the spike being up. Does it have to do with injection charge as we switch the transistor? I changed the rise and fall time of the clock for slower times(from 10p to 100n) and these transitions were gone, which made me think it might have something to do with the capacitor.

    Sorry if my english is not the best, im not a native speaker.

    Kind Regards,

    Francisco
     
  2. joeyd999

    AAC Fanatic!

    Jun 6, 2011
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    Charge injection is the likely culprit, but I would expect the step size to be the same regardless of clock speed for a given Vgs step.

    Also, assuming the gate capacitance is the same for each FET, the charge injection contributed by each part should cancel, I believe.
     
  3. joeyd999

    AAC Fanatic!

    Jun 6, 2011
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    Your graph only shows Vck, but not Vnck. Are they anti-symmetrical (as they should be)?
     
  4. Luce Sky Walker

    Thread Starter New Member

    Feb 17, 2017
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    0
    Yes
     
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