Hey guys,
I've tossed together a circuit to mess around with dynamic CMOS logic...however, when I pass the output into a voltage follower (+ terminal, - terminal is feedback), it works fine when the output is high on the low clock cycle, but on the high clock cycle, the NAND gate "evaluates" to a 0, and the output voltage reduces at the + terminal, but not at the - terminal. I thought that the op-amp amplified based on the difference of voltage, so when the + voltage quickly reduces, the feedback to the - terminal would be negative?
Here is the circuit: http://tinyurl.com/uod8vt7
Thanks!
I've tossed together a circuit to mess around with dynamic CMOS logic...however, when I pass the output into a voltage follower (+ terminal, - terminal is feedback), it works fine when the output is high on the low clock cycle, but on the high clock cycle, the NAND gate "evaluates" to a 0, and the output voltage reduces at the + terminal, but not at the - terminal. I thought that the op-amp amplified based on the difference of voltage, so when the + voltage quickly reduces, the feedback to the - terminal would be negative?
Here is the circuit: http://tinyurl.com/uod8vt7
Thanks!