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need a program for different faults like ssa(0/1),delay fault, bridge etc.
Vhdl program
- Thread starter divyasharma
- Start date
What? I think there is no way to induce faults in VHDL design, apart from acutally typing the errors inside your code.
If you are trying to verify your design based on possible faults, there may be some tools for that, but I think this would be better done on a piece of paper.
If you are trying to verify your design based on possible faults, there may be some tools for that, but I think this would be better done on a piece of paper.
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